The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 28GHz 대역 고선형 적층형 FET 전력 증폭기(PA) IC를 소개합니다. 스케일링된 MOSFET 트랜지스터의 낮은 항복 전압을 고려하여 높은 출력 전력을 위해 4-Stacked-FET 구조를 사용합니다. 증폭 MOSFET의 게이트-소스 바이어스 전압을 동적으로 제어하기 위한 새로운 적응형 바이어스 회로가 제안되었습니다. 새로운 적응형 바이어스를 통해 PA는 높은 백오프 효율로 높은 선형성을 달성할 수 있습니다. 또한, 멀티 캐스코드 구조를 통해 3차 상호변조 왜곡(IM56)을 개선하였다. PA IC는 4nm SOI CMOS 기술로 설계, 제작 및 완벽하게 테스트되었습니다. 20.0V의 공급 전압에서 PA IC는 38.1dB 이득 압축 지점(P1dB)에서 1%의 높은 PAE로 3dBm의 출력 전력을 달성했습니다. 더욱이, P6dB로부터 1dB 및 36.2dB 백오프에서의 PAE는 각각 28.7% 및 3%입니다. PA IC는 25.0dBm의 출력 OIPXNUMX(XNUMX차 차단점)을 나타냅니다.
Cuilin CHEN
Waseda University
Tsuyoshi SUGIURA
Samsung R&D Institute Japan
Toshihiko YOSHIMASU
Waseda University
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부
Cuilin CHEN, Tsuyoshi SUGIURA, Toshihiko YOSHIMASU, "A 28-GHz-Band Highly Linear Stacked-FET Power Amplifier IC with High Back-Off PAE in 56-nm SOI CMOS" in IEICE TRANSACTIONS on Electronics,
vol. E103-C, no. 4, pp. 153-160, April 2020, doi: 10.1587/transele.2019CDP0003.
Abstract: This paper presents a 28-GHz-band highly linear stacked-FET power amplifier (PA) IC. A 4-stacked-FET structure is employed for high output power considering the low breakdown voltage of scaled MOSFET transistors. A novel adaptive bias circuit is proposed to dynamically control the gate-to-source bias voltage for amplification MOSFETs. The novel adaptive bias allows the PA to attain high linearity with high back-off efficiency. In addition, the third-order intermodulation distortion (IM3) is improved by a multi-cascode structure. The PA IC is designed, fabricated and fully tested in 56-nm SOI CMOS technology. At a supply voltage of 4 V, the PA IC has achieved an output power of 20.0 dBm with a PAE as high as 38.1% at the 1-dB gain compression point (P1dB). Moreover, PAEs at 3-dB and 6-dB back-off from P1dB are 36.2% and 28.7%, respectively. The PA IC exhibits an output third-order intercept point (OIP3) of 25.0 dBm.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2019CDP0003/_p
부
@ARTICLE{e103-c_4_153,
author={Cuilin CHEN, Tsuyoshi SUGIURA, Toshihiko YOSHIMASU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 28-GHz-Band Highly Linear Stacked-FET Power Amplifier IC with High Back-Off PAE in 56-nm SOI CMOS},
year={2020},
volume={E103-C},
number={4},
pages={153-160},
abstract={This paper presents a 28-GHz-band highly linear stacked-FET power amplifier (PA) IC. A 4-stacked-FET structure is employed for high output power considering the low breakdown voltage of scaled MOSFET transistors. A novel adaptive bias circuit is proposed to dynamically control the gate-to-source bias voltage for amplification MOSFETs. The novel adaptive bias allows the PA to attain high linearity with high back-off efficiency. In addition, the third-order intermodulation distortion (IM3) is improved by a multi-cascode structure. The PA IC is designed, fabricated and fully tested in 56-nm SOI CMOS technology. At a supply voltage of 4 V, the PA IC has achieved an output power of 20.0 dBm with a PAE as high as 38.1% at the 1-dB gain compression point (P1dB). Moreover, PAEs at 3-dB and 6-dB back-off from P1dB are 36.2% and 28.7%, respectively. The PA IC exhibits an output third-order intercept point (OIP3) of 25.0 dBm.},
keywords={},
doi={10.1587/transele.2019CDP0003},
ISSN={1745-1353},
month={April},}
부
TY - JOUR
TI - A 28-GHz-Band Highly Linear Stacked-FET Power Amplifier IC with High Back-Off PAE in 56-nm SOI CMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 153
EP - 160
AU - Cuilin CHEN
AU - Tsuyoshi SUGIURA
AU - Toshihiko YOSHIMASU
PY - 2020
DO - 10.1587/transele.2019CDP0003
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E103-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2020
AB - This paper presents a 28-GHz-band highly linear stacked-FET power amplifier (PA) IC. A 4-stacked-FET structure is employed for high output power considering the low breakdown voltage of scaled MOSFET transistors. A novel adaptive bias circuit is proposed to dynamically control the gate-to-source bias voltage for amplification MOSFETs. The novel adaptive bias allows the PA to attain high linearity with high back-off efficiency. In addition, the third-order intermodulation distortion (IM3) is improved by a multi-cascode structure. The PA IC is designed, fabricated and fully tested in 56-nm SOI CMOS technology. At a supply voltage of 4 V, the PA IC has achieved an output power of 20.0 dBm with a PAE as high as 38.1% at the 1-dB gain compression point (P1dB). Moreover, PAEs at 3-dB and 6-dB back-off from P1dB are 36.2% and 28.7%, respectively. The PA IC exhibits an output third-order intercept point (OIP3) of 25.0 dBm.
ER -