The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 개선된 전하 펌프(CP)와 수정된 비선형 위상 주파수 검출기(PFD)를 90nm CMOS 공정에서 설계하고 제작했습니다. CP는 전하 주입 및 기타 비이상적 특성을 제거하기 위해 페데스탈 오류 제거 방식과 같은 회로 기술의 조합으로 최적화되었습니다. 비선형 PFD는 PLL의 획득 기능을 향상시키기 위해 수정된 회로 토폴로지를 기반으로 합니다. 최적화된 CP와 비선형 PFD는 Ka 대역 PLL에 통합되어 있습니다. 개선된 CP의 측정된 출력 전류 불일치 비율은 출력 전압이 1% 미만입니다. V아웃 0.2V 전원 공급 장치에서 1.1~1.2V 사이에서 변동합니다. 수정된 비선형 PFD의 측정된 위상 오류 감지 범위는 -2π와 2π 사이입니다. 수정된 CP 및 PFD로 인해 최적화된 CP 및 PFD를 포함하는 Ka 대역 PLL 주파수 합성기의 측정된 기준 스퍼는 잠금 상태의 56.409GHz에서 -30dBc에 불과합니다.
Lu TANG
Southeast University
Zhigong WANG
Southeast University
Tiantian FAN
Southeast University
Faen LIU
Southeast University
Changchun ZHANG
Nanjing University of Posts and Telecommunications
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부
Lu TANG, Zhigong WANG, Tiantian FAN, Faen LIU, Changchun ZHANG, "Optimized Charge Pump and Nonlinear Phase Frequency Detector for a Ka-Band Phase-Locked Loop in 90-nm CMOS Process" in IEICE TRANSACTIONS on Electronics,
vol. E102-C, no. 11, pp. 825-832, November 2019, doi: 10.1587/transele.2019ECP5007.
Abstract: In this paper, an improved charge pump (CP) and a modified nonlinear phase frequency detector (PFD) are designed and fabricated in a 90-nm CMOS process. The CP is optimized with a combination of circuit techniques such as pedestal error cancel scheme to eliminate the charge injection and the other non-ideal characteristics. The nonlinear PFD is based on a modified circuit topology to enhance the acquisition capability of the PLL. The optimized CP and nonlinear PFD are integrated into a Ka-band PLL. The measured output current mismatch ratio of the improved CP is less than 1% when the output voltage Vout fluctuates between 0.2 to 1.1V from a 1.2V power supply. The measured phase error detection range of the modified nonlinear PFD is between -2π and 2π. Owing to the modified CP and PFD, the measured reference spur of the Ka-band PLL frequency synthesizer containing the optimized CP and PFD is only -56.409dBc at 30-GHz at the locked state.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2019ECP5007/_p
부
@ARTICLE{e102-c_11_825,
author={Lu TANG, Zhigong WANG, Tiantian FAN, Faen LIU, Changchun ZHANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Optimized Charge Pump and Nonlinear Phase Frequency Detector for a Ka-Band Phase-Locked Loop in 90-nm CMOS Process},
year={2019},
volume={E102-C},
number={11},
pages={825-832},
abstract={In this paper, an improved charge pump (CP) and a modified nonlinear phase frequency detector (PFD) are designed and fabricated in a 90-nm CMOS process. The CP is optimized with a combination of circuit techniques such as pedestal error cancel scheme to eliminate the charge injection and the other non-ideal characteristics. The nonlinear PFD is based on a modified circuit topology to enhance the acquisition capability of the PLL. The optimized CP and nonlinear PFD are integrated into a Ka-band PLL. The measured output current mismatch ratio of the improved CP is less than 1% when the output voltage Vout fluctuates between 0.2 to 1.1V from a 1.2V power supply. The measured phase error detection range of the modified nonlinear PFD is between -2π and 2π. Owing to the modified CP and PFD, the measured reference spur of the Ka-band PLL frequency synthesizer containing the optimized CP and PFD is only -56.409dBc at 30-GHz at the locked state.},
keywords={},
doi={10.1587/transele.2019ECP5007},
ISSN={1745-1353},
month={November},}
부
TY - JOUR
TI - Optimized Charge Pump and Nonlinear Phase Frequency Detector for a Ka-Band Phase-Locked Loop in 90-nm CMOS Process
T2 - IEICE TRANSACTIONS on Electronics
SP - 825
EP - 832
AU - Lu TANG
AU - Zhigong WANG
AU - Tiantian FAN
AU - Faen LIU
AU - Changchun ZHANG
PY - 2019
DO - 10.1587/transele.2019ECP5007
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E102-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2019
AB - In this paper, an improved charge pump (CP) and a modified nonlinear phase frequency detector (PFD) are designed and fabricated in a 90-nm CMOS process. The CP is optimized with a combination of circuit techniques such as pedestal error cancel scheme to eliminate the charge injection and the other non-ideal characteristics. The nonlinear PFD is based on a modified circuit topology to enhance the acquisition capability of the PLL. The optimized CP and nonlinear PFD are integrated into a Ka-band PLL. The measured output current mismatch ratio of the improved CP is less than 1% when the output voltage Vout fluctuates between 0.2 to 1.1V from a 1.2V power supply. The measured phase error detection range of the modified nonlinear PFD is between -2π and 2π. Owing to the modified CP and PFD, the measured reference spur of the Ka-band PLL frequency synthesizer containing the optimized CP and PFD is only -56.409dBc at 30-GHz at the locked state.
ER -