The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
전기적 활성 소자의 노화로 인한 SiC-MOSFET 기반 DC-AC 컨버터-회로 효율 저하를 조사합니다. 고전압 SiC-MOSFET용으로 새로 개발된 소형 에이징 모델 HiSIM_HSiC가 조사에 사용되었습니다. 모델은 포아송 방정식의 해에서 캐리어 트랩 밀도 증가를 명시적으로 고려합니다. 3상 선-접지(3LG) 결함 중에 측정된 컨버터 특성이 모델에 의해 올바르게 재현됩니다. 결함 이벤트 중에 발생하는 높은 바이어스로 인해 MOSFET이 추가적인 스트레스를 경험하고, 이는 심각한 MOSFET 노화로 이어지는 것으로 확인되었습니다. 시뮬레이션 결과는 단일 0.5ms-70LG로 인해 컨버터 효율이 3% 감소할 것으로 예측합니다. 이는 추가 스트레스가 적용되지 않는 정상 조건에서 XNUMX년 동안 작동하는 것과 같습니다. 개발된 컴팩트 모델을 사용하면 측정이 어렵고 일반적으로 사용할 수 없는 장기간 스트레스 하에서 컨버터 회로의 효율 저하를 예측하는 것도 가능합니다.
Kenshiro SATO
Hiroshima University
Dondee NAVARRO
Hiroshima University
Shinya SEKIZAKI
Hiroshima University
Yoshifumi ZOKA
Hiroshima University
Naoto YORINO
Hiroshima University
Hans Jürgen MATTAUSCH
Hiroshima University
Mitiko MIURA-MATTAUSCH
Hiroshima University
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Kenshiro SATO, Dondee NAVARRO, Shinya SEKIZAKI, Yoshifumi ZOKA, Naoto YORINO, Hans Jürgen MATTAUSCH, Mitiko MIURA-MATTAUSCH, "Prediction of DC-AC Converter Efficiency Degradation due to Device Aging Using a Compact MOSFET-Aging Model" in IEICE TRANSACTIONS on Electronics,
vol. E103-C, no. 3, pp. 119-126, March 2020, doi: 10.1587/transele.2019ECP5010.
Abstract: The degradation of a SiC-MOSFET-based DC-AC converter-circuit efficiency due to aging of the electrically active devices is investigated. The newly developed compact aging model HiSIM_HSiC for high-voltage SiC-MOSFETs is used in the investigation. The model considers explicitly the carrier-trap-density increase in the solution of the Poisson equation. Measured converter characteristics during a 3-phase line-to-ground (3LG) fault is correctly reproduced by the model. It is verified that the MOSFETs experience additional stress due to the high biases occurring during the fault event, which translates to severe MOSFET aging. Simulation results predict a 0.5% reduction of converter efficiency due to a single 70ms-3LG, which is equivalent to a year of operation under normal conditions, where no additional stress is applied. With the developed compact model, prediction of the efficiency degradation of the converter circuit under prolonged stress, for which measurements are difficult to obtain and typically not available, is also feasible.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2019ECP5010/_p
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@ARTICLE{e103-c_3_119,
author={Kenshiro SATO, Dondee NAVARRO, Shinya SEKIZAKI, Yoshifumi ZOKA, Naoto YORINO, Hans Jürgen MATTAUSCH, Mitiko MIURA-MATTAUSCH, },
journal={IEICE TRANSACTIONS on Electronics},
title={Prediction of DC-AC Converter Efficiency Degradation due to Device Aging Using a Compact MOSFET-Aging Model},
year={2020},
volume={E103-C},
number={3},
pages={119-126},
abstract={The degradation of a SiC-MOSFET-based DC-AC converter-circuit efficiency due to aging of the electrically active devices is investigated. The newly developed compact aging model HiSIM_HSiC for high-voltage SiC-MOSFETs is used in the investigation. The model considers explicitly the carrier-trap-density increase in the solution of the Poisson equation. Measured converter characteristics during a 3-phase line-to-ground (3LG) fault is correctly reproduced by the model. It is verified that the MOSFETs experience additional stress due to the high biases occurring during the fault event, which translates to severe MOSFET aging. Simulation results predict a 0.5% reduction of converter efficiency due to a single 70ms-3LG, which is equivalent to a year of operation under normal conditions, where no additional stress is applied. With the developed compact model, prediction of the efficiency degradation of the converter circuit under prolonged stress, for which measurements are difficult to obtain and typically not available, is also feasible.},
keywords={},
doi={10.1587/transele.2019ECP5010},
ISSN={1745-1353},
month={March},}
부
TY - JOUR
TI - Prediction of DC-AC Converter Efficiency Degradation due to Device Aging Using a Compact MOSFET-Aging Model
T2 - IEICE TRANSACTIONS on Electronics
SP - 119
EP - 126
AU - Kenshiro SATO
AU - Dondee NAVARRO
AU - Shinya SEKIZAKI
AU - Yoshifumi ZOKA
AU - Naoto YORINO
AU - Hans Jürgen MATTAUSCH
AU - Mitiko MIURA-MATTAUSCH
PY - 2020
DO - 10.1587/transele.2019ECP5010
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E103-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2020
AB - The degradation of a SiC-MOSFET-based DC-AC converter-circuit efficiency due to aging of the electrically active devices is investigated. The newly developed compact aging model HiSIM_HSiC for high-voltage SiC-MOSFETs is used in the investigation. The model considers explicitly the carrier-trap-density increase in the solution of the Poisson equation. Measured converter characteristics during a 3-phase line-to-ground (3LG) fault is correctly reproduced by the model. It is verified that the MOSFETs experience additional stress due to the high biases occurring during the fault event, which translates to severe MOSFET aging. Simulation results predict a 0.5% reduction of converter efficiency due to a single 70ms-3LG, which is equivalent to a year of operation under normal conditions, where no additional stress is applied. With the developed compact model, prediction of the efficiency degradation of the converter circuit under prolonged stress, for which measurements are difficult to obtain and typically not available, is also feasible.
ER -