The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
추가는 많은 오류 허용 응용 프로그램의 핵심 기본 기능입니다. 대략적인 추가는 성능 및 정확성에 비해 에너지를 교환하는 효율적인 기술로 간주됩니다. 본 논문에서는 런타임에 정확도를 구성할 수 있는 캐리 마스크 가능 가산기를 제안합니다. 제안된 방식은 품질 요구 사항을 유연하게 충족하기 위해 캐리 전파 길이를 동적으로 선택할 수 있습니다. 제안하는 16비트 가산기는 기존 리플 캐리 가산기와 기존 캐리 미리보기 가산기에 비해 전력 소모를 각각 54.1%, 57.5% 감소시켰고, 임계 경로 지연을 각각 72.5%, 54.2% 감소시켰다. 또한, 이미지 처리 애플리케이션의 결과는 처리된 이미지의 품질이 제안된 가산기에 의해 제어될 수 있음을 나타냅니다. 제안한 가산기의 우수한 확장성은 32비트 길이를 사용한 평가 결과에서 입증된다.
Tongxin YANG
Fukuoka University
Toshinori SATO
Fukuoka University
Tomoaki UKEZONO
Fukuoka University
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부
Tongxin YANG, Toshinori SATO, Tomoaki UKEZONO, "An Accuracy-Configurable Adder for Low-Power Applications" in IEICE TRANSACTIONS on Electronics,
vol. E103-C, no. 3, pp. 68-76, March 2020, doi: 10.1587/transele.2019LHP0002.
Abstract: Addition is a key fundamental function for many error-tolerant applications. Approximate addition is considered to be an efficient technique for trading off energy against performance and accuracy. This paper proposes a carry-maskable adder whose accuracy can be configured at runtime. The proposed scheme can dynamically select the length of the carry propagation to satisfy the quality requirements flexibly. Compared with a conventional ripple carry adder and a conventional carry look-ahead adder, the proposed 16-bit adder reduced the power consumption by 54.1% and 57.5%, respectively, and the critical path delay by 72.5% and 54.2%, respectively. In addition, results from an image processing application indicate that the quality of processed images can be controlled by the proposed adder. Good scalability of the proposed adder is demonstrated from the evaluation results using a 32-bit length.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2019LHP0002/_p
부
@ARTICLE{e103-c_3_68,
author={Tongxin YANG, Toshinori SATO, Tomoaki UKEZONO, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Accuracy-Configurable Adder for Low-Power Applications},
year={2020},
volume={E103-C},
number={3},
pages={68-76},
abstract={Addition is a key fundamental function for many error-tolerant applications. Approximate addition is considered to be an efficient technique for trading off energy against performance and accuracy. This paper proposes a carry-maskable adder whose accuracy can be configured at runtime. The proposed scheme can dynamically select the length of the carry propagation to satisfy the quality requirements flexibly. Compared with a conventional ripple carry adder and a conventional carry look-ahead adder, the proposed 16-bit adder reduced the power consumption by 54.1% and 57.5%, respectively, and the critical path delay by 72.5% and 54.2%, respectively. In addition, results from an image processing application indicate that the quality of processed images can be controlled by the proposed adder. Good scalability of the proposed adder is demonstrated from the evaluation results using a 32-bit length.},
keywords={},
doi={10.1587/transele.2019LHP0002},
ISSN={1745-1353},
month={March},}
부
TY - JOUR
TI - An Accuracy-Configurable Adder for Low-Power Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 68
EP - 76
AU - Tongxin YANG
AU - Toshinori SATO
AU - Tomoaki UKEZONO
PY - 2020
DO - 10.1587/transele.2019LHP0002
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E103-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2020
AB - Addition is a key fundamental function for many error-tolerant applications. Approximate addition is considered to be an efficient technique for trading off energy against performance and accuracy. This paper proposes a carry-maskable adder whose accuracy can be configured at runtime. The proposed scheme can dynamically select the length of the carry propagation to satisfy the quality requirements flexibly. Compared with a conventional ripple carry adder and a conventional carry look-ahead adder, the proposed 16-bit adder reduced the power consumption by 54.1% and 57.5%, respectively, and the critical path delay by 72.5% and 54.2%, respectively. In addition, results from an image processing application indicate that the quality of processed images can be controlled by the proposed adder. Good scalability of the proposed adder is demonstrated from the evaluation results using a 32-bit length.
ER -