The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 p-well과 n-well 바이어스를 독립적으로 제어하는 최소 에너지 동작을 위한 면적 및 에너지 효율적인 DLL 기반 BBG(Body Bias Generator)를 제안합니다. BBG는 nMOSFET과 pMOSFET 간의 왜곡된 프로세스 조건에서 대상 회로의 총 에너지 소비를 최소화할 수 있습니다. 제안된 BBG는 셀 기반 설계와 호환되는 디지털 셀로 구성되어 추가 공급 전압 없이 에너지 및 공간 효율적인 구현이 가능합니다. 테스트 회로는 65nm FDSOI 프로세스로 구현되었습니다. 동일한 칩에 32비트 RISC 프로세서를 사용한 측정 결과, 제안된 BBG는 3% 에너지 손실 내에서 최소에 가깝게 에너지 소비를 줄일 수 있음을 보여줍니다. 이 조건에서 BBG의 에너지 오버헤드와 면적 오버헤드는 각각 0.2%와 0.12%입니다.
Kentaro NAGAI
Kyoto University
Jun SHIOMI
Kyoto University
Hidetoshi ONODERA
Kyoto University
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Kentaro NAGAI, Jun SHIOMI, Hidetoshi ONODERA, "A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation" in IEICE TRANSACTIONS on Electronics,
vol. E104-C, no. 10, pp. 617-624, October 2021, doi: 10.1587/transele.2020CTP0002.
Abstract: This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently. The BBG can minimize total energy consumption of target circuits under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which enables energy- and area-efficient implementation without additional supply voltages. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor on the same chip show that the proposed BBG can reduce energy consumption close to a minimum within a 3% energy loss. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2020CTP0002/_p
부
@ARTICLE{e104-c_10_617,
author={Kentaro NAGAI, Jun SHIOMI, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation},
year={2021},
volume={E104-C},
number={10},
pages={617-624},
abstract={This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently. The BBG can minimize total energy consumption of target circuits under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which enables energy- and area-efficient implementation without additional supply voltages. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor on the same chip show that the proposed BBG can reduce energy consumption close to a minimum within a 3% energy loss. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.},
keywords={},
doi={10.1587/transele.2020CTP0002},
ISSN={1745-1353},
month={October},}
부
TY - JOUR
TI - A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation
T2 - IEICE TRANSACTIONS on Electronics
SP - 617
EP - 624
AU - Kentaro NAGAI
AU - Jun SHIOMI
AU - Hidetoshi ONODERA
PY - 2021
DO - 10.1587/transele.2020CTP0002
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E104-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2021
AB - This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently. The BBG can minimize total energy consumption of target circuits under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which enables energy- and area-efficient implementation without additional supply voltages. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor on the same chip show that the proposed BBG can reduce energy consumption close to a minimum within a 3% energy loss. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.
ER -