The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 CMOS 이미지 센서(CIS) 칩의 ADC 및 램프 생성기의 고정밀 측정을 위한 새로운 테스트 기술을 제안합니다. ADC의 테스트 회로에는 이중 경로가 있으며 각 열에 대한 입력을 정의하여 CIS 특정 특성을 전기적으로 평가할 수 있는 다기능 미세 패턴 생성기 기능이 있습니다. 램프 생성기용 테스트 회로는 온칩 전류 셀 테스트를 실현하고 1LSB 정확도 내에서 현재 셀 오류를 거부할 수 있습니다. 55nm CIS 공정을 이용하여 테스트 센서를 제작하고 IP 특성을 측정했습니다. 측정 결과 INL은 14.6LSB, 누화는 14.9LSB, 열 간섭 잡음은 5.4LSB로 나타났습니다. 이러한 측정 결과는 설계된 값과 일치합니다. 이 기술을 사용함으로써 광입력의 모호성에 영향을 받지 않고 정확한 ADC 측정이 구현될 수 있음을 확인했습니다.
Fukashi MORISHITA
Renesas Electronics Corporation
Wataru SAITO
Renesas Electronics Corporation
Norihito KATO
Renesas Electronics Corporation
Yoichi IIZUKA
Renesas Electronics Corporation
Masao ITO
Renesas Electronics Corporation
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Fukashi MORISHITA, Wataru SAITO, Norihito KATO, Yoichi IIZUKA, Masao ITO, "High Accuracy Test Techniques with Fine Pattern Generator and Ramp Test Circuit for CMOS Image Sensor" in IEICE TRANSACTIONS on Electronics,
vol. E105-C, no. 7, pp. 316-323, July 2022, doi: 10.1587/transele.2021CDP0001.
Abstract: This paper proposes novel test techniques for high accuracy measurement of ADCs and a ramp generator on a CMOS image sensor (CIS) chip. The test circuit for the ADCs has a dual path and has an ability of multi-functional fine pattern generator that can define any input for each column to evaluate CIS specific characteristics electrically. The test circuit for the ramp generator can realize an on-chip current cell test and reject the current cell failure within 1LSB accuracy. We fabricated the test sensor using 55nm CIS process and measured the IP characteristics. Measured results show INL of 14.6LSB, crosstalk of 14.9LSB and column interference noise of 5.4LSB. These measured results agree with the designed values. By using this technique, we confirmed the accurate ADC measurement can be realized without being affected by the ambiguity of the optical input.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2021CDP0001/_p
부
@ARTICLE{e105-c_7_316,
author={Fukashi MORISHITA, Wataru SAITO, Norihito KATO, Yoichi IIZUKA, Masao ITO, },
journal={IEICE TRANSACTIONS on Electronics},
title={High Accuracy Test Techniques with Fine Pattern Generator and Ramp Test Circuit for CMOS Image Sensor},
year={2022},
volume={E105-C},
number={7},
pages={316-323},
abstract={This paper proposes novel test techniques for high accuracy measurement of ADCs and a ramp generator on a CMOS image sensor (CIS) chip. The test circuit for the ADCs has a dual path and has an ability of multi-functional fine pattern generator that can define any input for each column to evaluate CIS specific characteristics electrically. The test circuit for the ramp generator can realize an on-chip current cell test and reject the current cell failure within 1LSB accuracy. We fabricated the test sensor using 55nm CIS process and measured the IP characteristics. Measured results show INL of 14.6LSB, crosstalk of 14.9LSB and column interference noise of 5.4LSB. These measured results agree with the designed values. By using this technique, we confirmed the accurate ADC measurement can be realized without being affected by the ambiguity of the optical input.},
keywords={},
doi={10.1587/transele.2021CDP0001},
ISSN={1745-1353},
month={July},}
부
TY - JOUR
TI - High Accuracy Test Techniques with Fine Pattern Generator and Ramp Test Circuit for CMOS Image Sensor
T2 - IEICE TRANSACTIONS on Electronics
SP - 316
EP - 323
AU - Fukashi MORISHITA
AU - Wataru SAITO
AU - Norihito KATO
AU - Yoichi IIZUKA
AU - Masao ITO
PY - 2022
DO - 10.1587/transele.2021CDP0001
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E105-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2022
AB - This paper proposes novel test techniques for high accuracy measurement of ADCs and a ramp generator on a CMOS image sensor (CIS) chip. The test circuit for the ADCs has a dual path and has an ability of multi-functional fine pattern generator that can define any input for each column to evaluate CIS specific characteristics electrically. The test circuit for the ramp generator can realize an on-chip current cell test and reject the current cell failure within 1LSB accuracy. We fabricated the test sensor using 55nm CIS process and measured the IP characteristics. Measured results show INL of 14.6LSB, crosstalk of 14.9LSB and column interference noise of 5.4LSB. These measured results agree with the designed values. By using this technique, we confirmed the accurate ADC measurement can be realized without being affected by the ambiguity of the optical input.
ER -