The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 회로의 복잡성과 전력 소비를 증가시키지 않고 THz 미만 대역에서 작동하는 CMOS 주파수 체배기의 성능을 향상시키는 여러 가지 설계 기술을 소개합니다. 제안된 기법은 장치 비선형성 기반 주파수 삼중기와 푸시-푸시 주파수 삼중기에 적용된다. 기본 및 2.9차 고조파 피드백 제거 기능을 활용하여 트리플러는 필요한 면적과 전력 소비를 줄이는 간단한 단일 종단 회로 아키텍처로 -103dBm 출력 전력을 달성합니다. 트리플러는 130~2.3GHz의 주파수에서 작동합니다. 도입된 수정된 푸시-푸시 더블러는 발룬 손실을 포함하여 118dB 변환 이득을 제공하며 발룬 불일치에 대한 내성이 뛰어납니다. 더블러의 출력 주파수는 124GHz ~ 65GHz입니다. 두 회로 모두 CMOS XNUMXnm 기술을 사용하여 설계 및 제작되었습니다.
Ibrahim ABDO
Tokyo Institute of Technology
Korkut Kaan TOKGOZ
Tokyo Institute of Technology
Atsushi SHIRANE
Tokyo Institute of Technology
Kenichi OKADA
Tokyo Institute of Technology
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Ibrahim ABDO, Korkut Kaan TOKGOZ, Atsushi SHIRANE, Kenichi OKADA, "F-band Frequency Multipliers with Fundamental and Harmonic Rejection for Improved Conversion Gain and Output Power" in IEICE TRANSACTIONS on Electronics,
vol. E105-C, no. 3, pp. 118-125, March 2022, doi: 10.1587/transele.2021ECP5036.
Abstract: This paper introduces several design techniques to improve the performance of CMOS frequency multipliers that operate at the sub-THz band without increasing the complexity and the power consumption of the circuit. The proposed techniques are applied to a device nonlinearity-based frequency tripler and to a push-push frequency doubler. By utilizing the fundamental and second harmonic feedback cancellation, the tripler achieves -2.9dBm output power with a simple single-ended circuit architecture reducing the required area and power consumption. The tripler operates at frequencies from 103GHz to 130GHz. The introduced modified push-push doubler provides 2.3dB conversion gain including the balun losses and it has good tolerance against balun mismatches. The output frequency of the doubler is from 118GHz to 124GHz. Both circuits were designed and fabricated using CMOS 65nm technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2021ECP5036/_p
부
@ARTICLE{e105-c_3_118,
author={Ibrahim ABDO, Korkut Kaan TOKGOZ, Atsushi SHIRANE, Kenichi OKADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={F-band Frequency Multipliers with Fundamental and Harmonic Rejection for Improved Conversion Gain and Output Power},
year={2022},
volume={E105-C},
number={3},
pages={118-125},
abstract={This paper introduces several design techniques to improve the performance of CMOS frequency multipliers that operate at the sub-THz band without increasing the complexity and the power consumption of the circuit. The proposed techniques are applied to a device nonlinearity-based frequency tripler and to a push-push frequency doubler. By utilizing the fundamental and second harmonic feedback cancellation, the tripler achieves -2.9dBm output power with a simple single-ended circuit architecture reducing the required area and power consumption. The tripler operates at frequencies from 103GHz to 130GHz. The introduced modified push-push doubler provides 2.3dB conversion gain including the balun losses and it has good tolerance against balun mismatches. The output frequency of the doubler is from 118GHz to 124GHz. Both circuits were designed and fabricated using CMOS 65nm technology.},
keywords={},
doi={10.1587/transele.2021ECP5036},
ISSN={1745-1353},
month={March},}
부
TY - JOUR
TI - F-band Frequency Multipliers with Fundamental and Harmonic Rejection for Improved Conversion Gain and Output Power
T2 - IEICE TRANSACTIONS on Electronics
SP - 118
EP - 125
AU - Ibrahim ABDO
AU - Korkut Kaan TOKGOZ
AU - Atsushi SHIRANE
AU - Kenichi OKADA
PY - 2022
DO - 10.1587/transele.2021ECP5036
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E105-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2022
AB - This paper introduces several design techniques to improve the performance of CMOS frequency multipliers that operate at the sub-THz band without increasing the complexity and the power consumption of the circuit. The proposed techniques are applied to a device nonlinearity-based frequency tripler and to a push-push frequency doubler. By utilizing the fundamental and second harmonic feedback cancellation, the tripler achieves -2.9dBm output power with a simple single-ended circuit architecture reducing the required area and power consumption. The tripler operates at frequencies from 103GHz to 130GHz. The introduced modified push-push doubler provides 2.3dB conversion gain including the balun losses and it has good tolerance against balun mismatches. The output frequency of the doubler is from 118GHz to 124GHz. Both circuits were designed and fabricated using CMOS 65nm technology.
ER -