The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 다음 중 하나를 계산하는 체계를 제시합니다. AB or AB2 곱셈 끝 GF(2m) 제안된 알고리즘을 기반으로 비트 병렬 수축기 아키텍처를 제안합니다. 그만큼 AB 곱셈 알고리즘은 다음의 공식과 같은 형태로 도출됩니다. AB2 곱셈 알고리즘과 이를 수행할 수 있는 아키텍처 AB 아주 약간의 추가 하드웨어를 추가하여 곱셈 AB2 승수가 설계되었습니다. 따라서 제안된 아키텍처는 배포가 불가능한 하드웨어 제약이 있는 애플리케이션에 효과적으로 적용될 수 있다. AB2 승수 및 AB 승수는 별도로.
Kee-Won KIM
Mokpo National Maritime University
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부
Kee-Won KIM, "Bit-Parallel Systolic Architecture for AB and AB2 Multiplications over GF(2m)" in IEICE TRANSACTIONS on Electronics,
vol. E105-C, no. 5, pp. 203-206, May 2022, doi: 10.1587/transele.2021ECS6006.
Abstract: In this paper, we present a scheme to compute either AB or AB2 multiplications over GF(2m) and propose a bit-parallel systolic architecture based on the proposed algorithm. The AB multiplication algorithm is derived in the same form as the formula of AB2 multiplication algorithm, and an architecture that can perform AB multiplication by adding very little extra hardware to AB2 multiplier is designed. Therefore, the proposed architecture can be effectively applied to hardware constrained applications that cannot deploy AB2 multiplier and AB multiplier separately.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2021ECS6006/_p
부
@ARTICLE{e105-c_5_203,
author={Kee-Won KIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={Bit-Parallel Systolic Architecture for AB and AB2 Multiplications over GF(2m)},
year={2022},
volume={E105-C},
number={5},
pages={203-206},
abstract={In this paper, we present a scheme to compute either AB or AB2 multiplications over GF(2m) and propose a bit-parallel systolic architecture based on the proposed algorithm. The AB multiplication algorithm is derived in the same form as the formula of AB2 multiplication algorithm, and an architecture that can perform AB multiplication by adding very little extra hardware to AB2 multiplier is designed. Therefore, the proposed architecture can be effectively applied to hardware constrained applications that cannot deploy AB2 multiplier and AB multiplier separately.},
keywords={},
doi={10.1587/transele.2021ECS6006},
ISSN={1745-1353},
month={May},}
부
TY - JOUR
TI - Bit-Parallel Systolic Architecture for AB and AB2 Multiplications over GF(2m)
T2 - IEICE TRANSACTIONS on Electronics
SP - 203
EP - 206
AU - Kee-Won KIM
PY - 2022
DO - 10.1587/transele.2021ECS6006
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E105-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2022
AB - In this paper, we present a scheme to compute either AB or AB2 multiplications over GF(2m) and propose a bit-parallel systolic architecture based on the proposed algorithm. The AB multiplication algorithm is derived in the same form as the formula of AB2 multiplication algorithm, and an architecture that can perform AB multiplication by adding very little extra hardware to AB2 multiplier is designed. Therefore, the proposed architecture can be effectively applied to hardware constrained applications that cannot deploy AB2 multiplier and AB multiplier separately.
ER -