The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 향상된 변조 대비를 갖춘 NIR 감도가 높은 SOI 게이트 잠금 픽셀을 제시합니다. 제안된 픽셀은 높은 측면 전기장과 기생 광 감도에 대한 잠재적 장벽을 생성하기 위해 얕은 매립 채널과 중간 게이트를 가지고 있습니다. 소자 시뮬레이션 결과, 기생 광 감도가 이전 구조에 비해 13.7%에서 0.13%로 감소한 것으로 나타났습니다.
Tatsuya KOBAYASHI
Shizuoka University
Keita YASUTOMI
Shizuoka University
Naoki TAKADA
Shizuoka University
Shoji KAWAHITO
Shizuoka University
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Tatsuya KOBAYASHI, Keita YASUTOMI, Naoki TAKADA, Shoji KAWAHITO, "An SOI-Based Lock-in Pixel with a Shallow Buried Channel for Reducing Parasitic Light Sensitivity and Improving Modulation Contrast" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 10, pp. 538-545, October 2023, doi: 10.1587/transele.2022CTP0003.
Abstract: This paper presents a high-NIR sensitivity SOI-gate lock-in pixel with improved modulation contrast. The proposed pixel has a shallow buried channel and intermediate gates to create both a high lateral electric field and a potential barrier to parasitic light sensitivity. Device simulation results showed that parasitic light sensitivity reduced from 13.7% to 0.13% compared to the previous structure.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022CTP0003/_p
부
@ARTICLE{e106-c_10_538,
author={Tatsuya KOBAYASHI, Keita YASUTOMI, Naoki TAKADA, Shoji KAWAHITO, },
journal={IEICE TRANSACTIONS on Electronics},
title={An SOI-Based Lock-in Pixel with a Shallow Buried Channel for Reducing Parasitic Light Sensitivity and Improving Modulation Contrast},
year={2023},
volume={E106-C},
number={10},
pages={538-545},
abstract={This paper presents a high-NIR sensitivity SOI-gate lock-in pixel with improved modulation contrast. The proposed pixel has a shallow buried channel and intermediate gates to create both a high lateral electric field and a potential barrier to parasitic light sensitivity. Device simulation results showed that parasitic light sensitivity reduced from 13.7% to 0.13% compared to the previous structure.},
keywords={},
doi={10.1587/transele.2022CTP0003},
ISSN={1745-1353},
month={October},}
부
TY - JOUR
TI - An SOI-Based Lock-in Pixel with a Shallow Buried Channel for Reducing Parasitic Light Sensitivity and Improving Modulation Contrast
T2 - IEICE TRANSACTIONS on Electronics
SP - 538
EP - 545
AU - Tatsuya KOBAYASHI
AU - Keita YASUTOMI
AU - Naoki TAKADA
AU - Shoji KAWAHITO
PY - 2023
DO - 10.1587/transele.2022CTP0003
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2023
AB - This paper presents a high-NIR sensitivity SOI-gate lock-in pixel with improved modulation contrast. The proposed pixel has a shallow buried channel and intermediate gates to create both a high lateral electric field and a potential barrier to parasitic light sensitivity. Device simulation results showed that parasitic light sensitivity reduced from 13.7% to 0.13% compared to the previous structure.
ER -