The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이중 모드 작동을 실현하기 위해 전력 확장이 가능한 SSPLL(위상 고정 루프)이 제안되었습니다. 위상 잡음이 좋은 고성능 모드와 위상 잡음이 보통인 절전 모드가 있습니다. 공급전압을 낮춰 전력소모를 줄이는 가장 효율적인 방법이다. 그러나 공급량이 적은 밀리미터파(mmW) SSPLL에는 몇 가지 문제가 있습니다. 이 연구에서는 CMOS DDC(Deep Depleted Channel Process)를 사용하는 것 외에도 백게이트 FBB(Forward Body Bias) 기술과 같은 몇 가지 기술에 대해 설명합니다.
Sangyeop LEE
Hiroshima University
Kyoya TAKANO
Hiroshima University
Shuhei AMAKAWA
Hiroshima University
Takeshi YOSHIDA
Hiroshima University
Minoru FUJISHIMA
Hiroshima University
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Sangyeop LEE, Kyoya TAKANO, Shuhei AMAKAWA, Takeshi YOSHIDA, Minoru FUJISHIMA, "A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 10, pp. 533-537, October 2023, doi: 10.1587/transele.2022CTS0001.
Abstract: A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022CTS0001/_p
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@ARTICLE{e106-c_10_533,
author={Sangyeop LEE, Kyoya TAKANO, Shuhei AMAKAWA, Takeshi YOSHIDA, Minoru FUJISHIMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC},
year={2023},
volume={E106-C},
number={10},
pages={533-537},
abstract={A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).},
keywords={},
doi={10.1587/transele.2022CTS0001},
ISSN={1745-1353},
month={October},}
부
TY - JOUR
TI - A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC
T2 - IEICE TRANSACTIONS on Electronics
SP - 533
EP - 537
AU - Sangyeop LEE
AU - Kyoya TAKANO
AU - Shuhei AMAKAWA
AU - Takeshi YOSHIDA
AU - Minoru FUJISHIMA
PY - 2023
DO - 10.1587/transele.2022CTS0001
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2023
AB - A power-scalable sub-sampling phase-locked loop (SSPLL) is proposed for realizing dual-mode operation; high-performance mode with good phase noise and power-saving mode with moderate phase noise. It is the most efficient way to reduce power consumption by lowering the supply voltage. However, there are several issues with the low-supply millimeter-wave (mmW) SSPLL. This work discusses some techniques, such as a back-gate forward body bias (FBB) technique, in addition to employing a CMOS deeply depleted channel process (DDC).
ER -