The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이 개요에서는 고속 비동기식 SAR(연속 근사 레지스터) ADC(아날로그-디지털 변환기)에 대한 SCA(부채널 공격) 기술을 소개합니다. 제안된 다중 잡음 파형 기반 이중 신경망은 미분 구조와 고속 비동기 연산으로 인해 숨겨졌던 입력 신호의 부호 및 절대값 정보를 개별적으로 공개한다. 대상 SAR ADC 및 온칩 잡음 모니터는 SCA 시연을 위해 단일 프로토타입 칩에 설계되었습니다. 40nm로 제작된 실험 결과는 비동기식 SAR ADC에 대해 제안된 공격이 300mV rms 오류 내에서 경쟁력 있는 정확도로 입력 데이터를 성공적으로 복원한다는 것을 보여줍니다.
Ryozo TAKAHASHI
Kobe University
Takuji MIKI
Kobe University
Makoto NAGATA
Kobe University
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Ryozo TAKAHASHI, Takuji MIKI, Makoto NAGATA, "An Analog Side-Channel Attack on a High-Speed Asynchronous SAR ADC Using Dual Neural Network Technique" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 10, pp. 565-569, October 2023, doi: 10.1587/transele.2022CTS0002.
Abstract: This brief presents a side-channel attack (SCA) technique on a high-speed asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed dual neural network based on multiple noise waveforms separately discloses sign and absolute value information of input signals which are hidden by the differential structure and high-speed asynchronous operation. The target SAR ADC and on-chip noise monitors are designed on a single prototype chip for SCA demonstration. Fabricated in 40 nm, the experimental results show the proposed attack on the asynchronous SAR ADC successfully restores the input data with a competitive accuracy within 300 mV rms error.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022CTS0002/_p
부
@ARTICLE{e106-c_10_565,
author={Ryozo TAKAHASHI, Takuji MIKI, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Analog Side-Channel Attack on a High-Speed Asynchronous SAR ADC Using Dual Neural Network Technique},
year={2023},
volume={E106-C},
number={10},
pages={565-569},
abstract={This brief presents a side-channel attack (SCA) technique on a high-speed asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed dual neural network based on multiple noise waveforms separately discloses sign and absolute value information of input signals which are hidden by the differential structure and high-speed asynchronous operation. The target SAR ADC and on-chip noise monitors are designed on a single prototype chip for SCA demonstration. Fabricated in 40 nm, the experimental results show the proposed attack on the asynchronous SAR ADC successfully restores the input data with a competitive accuracy within 300 mV rms error.},
keywords={},
doi={10.1587/transele.2022CTS0002},
ISSN={1745-1353},
month={October},}
부
TY - JOUR
TI - An Analog Side-Channel Attack on a High-Speed Asynchronous SAR ADC Using Dual Neural Network Technique
T2 - IEICE TRANSACTIONS on Electronics
SP - 565
EP - 569
AU - Ryozo TAKAHASHI
AU - Takuji MIKI
AU - Makoto NAGATA
PY - 2023
DO - 10.1587/transele.2022CTS0002
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2023
AB - This brief presents a side-channel attack (SCA) technique on a high-speed asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed dual neural network based on multiple noise waveforms separately discloses sign and absolute value information of input signals which are hidden by the differential structure and high-speed asynchronous operation. The target SAR ADC and on-chip noise monitors are designed on a single prototype chip for SCA demonstration. Fabricated in 40 nm, the experimental results show the proposed attack on the asynchronous SAR ADC successfully restores the input data with a competitive accuracy within 300 mV rms error.
ER -