The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
마스터-슬레이브 전환 커패시터를 기반으로 하는 파이프라인 레지스터를 사용하여 구성되는 완전 아날로그 파이프라인 심층 신경망(DNN) 가속기가 제안됩니다. 마스터-슬레이브 전환 커패시터의 개념은 디지털 파이프라인 레지스터로 사용되었던 지연 플립플롭(D-FF)과 동등한 아날로그입니다. 파이프라인 레지스터의 성능을 추정하기 위해 비파이프라인 작업을 수행하는 기존 DNN에 적용됩니다. 기존 DNN 대비 사이클 타임은 61.5% 단축되고 데이터 속도는 160% 향상된다. MNIST 분류 테스트에서는 정확도가 99.6%에 달합니다. 등급별 에너지 소비량은 88.2로 0.128% 감소µJ, 1.05의 에너지 효율 달성탑스/W 처리량은 0.538입니다.탑스 180nm 기술 노드에서.
Yaxin MEI
Waseda University
Takashi OHSAWA
Waseda University
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부
Yaxin MEI, Takashi OHSAWA, "A Fully Analog Deep Neural Network Inference Accelerator with Pipeline Registers Based on Master-Slave Switched Capacitors" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 9, pp. 477-485, September 2023, doi: 10.1587/transele.2022ECP5049.
Abstract: A fully analog pipelined deep neural network (DNN) accelerator is proposed, which is constructed by using pipeline registers based on master-slave switched capacitors. The idea of the master-slave switched capacitors is an analog equivalent of the delayed flip-flop (D-FF) which has been used as a digital pipeline register. To estimate the performance of the pipeline register, it is applied to a conventional DNN which performs non-pipeline operation. Compared with the conventional DNN, the cycle time is reduced by 61.5% and data rate is increased by 160%. The accuracy reaches 99.6% in MNIST classification test. The energy consumption per classification is reduced by 88.2% to 0.128µJ, achieving an energy efficiency of 1.05TOPS/W and a throughput of 0.538TOPS in 180nm technology node.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022ECP5049/_p
부
@ARTICLE{e106-c_9_477,
author={Yaxin MEI, Takashi OHSAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Fully Analog Deep Neural Network Inference Accelerator with Pipeline Registers Based on Master-Slave Switched Capacitors},
year={2023},
volume={E106-C},
number={9},
pages={477-485},
abstract={A fully analog pipelined deep neural network (DNN) accelerator is proposed, which is constructed by using pipeline registers based on master-slave switched capacitors. The idea of the master-slave switched capacitors is an analog equivalent of the delayed flip-flop (D-FF) which has been used as a digital pipeline register. To estimate the performance of the pipeline register, it is applied to a conventional DNN which performs non-pipeline operation. Compared with the conventional DNN, the cycle time is reduced by 61.5% and data rate is increased by 160%. The accuracy reaches 99.6% in MNIST classification test. The energy consumption per classification is reduced by 88.2% to 0.128µJ, achieving an energy efficiency of 1.05TOPS/W and a throughput of 0.538TOPS in 180nm technology node.},
keywords={},
doi={10.1587/transele.2022ECP5049},
ISSN={1745-1353},
month={September},}
부
TY - JOUR
TI - A Fully Analog Deep Neural Network Inference Accelerator with Pipeline Registers Based on Master-Slave Switched Capacitors
T2 - IEICE TRANSACTIONS on Electronics
SP - 477
EP - 485
AU - Yaxin MEI
AU - Takashi OHSAWA
PY - 2023
DO - 10.1587/transele.2022ECP5049
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2023
AB - A fully analog pipelined deep neural network (DNN) accelerator is proposed, which is constructed by using pipeline registers based on master-slave switched capacitors. The idea of the master-slave switched capacitors is an analog equivalent of the delayed flip-flop (D-FF) which has been used as a digital pipeline register. To estimate the performance of the pipeline register, it is applied to a conventional DNN which performs non-pipeline operation. Compared with the conventional DNN, the cycle time is reduced by 61.5% and data rate is increased by 160%. The accuracy reaches 99.6% in MNIST classification test. The energy consumption per classification is reduced by 88.2% to 0.128µJ, achieving an energy efficiency of 1.05TOPS/W and a throughput of 0.538TOPS in 180nm technology node.
ER -