The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 폴딩 및 보간 10-b ADC의 새로운 폴딩 증폭기를 소개합니다. 증폭기는 전류 미러와 차동 스테이지로 구성됩니다. 계단식 차동 쌍에서는 하나의 전류 소스만 활용되므로 전력 소비가 크게 줄어듭니다. 폴딩 회로에서는 전류 분할 기술을 사용하여 보간을 구현합니다. 10-b 폴딩 신호의 증폭기 실험은 단일 폴리 0.35금속 10μm CMOS 프로세스에 통합되었습니다. 225-b 폴딩 ADC의 시뮬레이션에서는 샘플링 속도 250 Msample/s 및 전원 공급 장치 3.3 V에서 전력 소비가 XNUMX mW임을 보여줍니다. 예비 실험에서는 전류 조정 폴더와 디지털 비트가 예상대로 작동함을 나타냅니다.
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Zhi-Yuan CUI, Yong-Gao JIN, Nam-Soo KIM, Ho-Yong CHOI, "Low Power 10-b 250 Msample/s CMOS Cascaded Folding and Interpolating A/D Converter" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 8, pp. 1073-1079, August 2009, doi: 10.1587/transele.E92.C.1073.
Abstract: This paper introduces a new folding amplifier in a folding and interpolating 10-b ADC. The amplifier consists of current mirrors and differential stages. Only one current source is exploited in cascaded differential pairs, which reduces the power consumption significantly. In the folding circuit, the interpolation is implemented with a current division technique. An experiment of the amplifier in 10-b folding signal has been integrated in a single-poly four-metal 0.35 µm CMOS process. The simulation in 10-b folding ADC shows that power consumption is 225 mW at the sampling speed of 250 Msample/s and the power supply of 3.3 V. The preliminary experiment indicates the current steering folder and digital bits operate as expected.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1073/_p
부
@ARTICLE{e92-c_8_1073,
author={Zhi-Yuan CUI, Yong-Gao JIN, Nam-Soo KIM, Ho-Yong CHOI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low Power 10-b 250 Msample/s CMOS Cascaded Folding and Interpolating A/D Converter},
year={2009},
volume={E92-C},
number={8},
pages={1073-1079},
abstract={This paper introduces a new folding amplifier in a folding and interpolating 10-b ADC. The amplifier consists of current mirrors and differential stages. Only one current source is exploited in cascaded differential pairs, which reduces the power consumption significantly. In the folding circuit, the interpolation is implemented with a current division technique. An experiment of the amplifier in 10-b folding signal has been integrated in a single-poly four-metal 0.35 µm CMOS process. The simulation in 10-b folding ADC shows that power consumption is 225 mW at the sampling speed of 250 Msample/s and the power supply of 3.3 V. The preliminary experiment indicates the current steering folder and digital bits operate as expected.},
keywords={},
doi={10.1587/transele.E92.C.1073},
ISSN={1745-1353},
month={August},}
부
TY - JOUR
TI - Low Power 10-b 250 Msample/s CMOS Cascaded Folding and Interpolating A/D Converter
T2 - IEICE TRANSACTIONS on Electronics
SP - 1073
EP - 1079
AU - Zhi-Yuan CUI
AU - Yong-Gao JIN
AU - Nam-Soo KIM
AU - Ho-Yong CHOI
PY - 2009
DO - 10.1587/transele.E92.C.1073
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2009
AB - This paper introduces a new folding amplifier in a folding and interpolating 10-b ADC. The amplifier consists of current mirrors and differential stages. Only one current source is exploited in cascaded differential pairs, which reduces the power consumption significantly. In the folding circuit, the interpolation is implemented with a current division technique. An experiment of the amplifier in 10-b folding signal has been integrated in a single-poly four-metal 0.35 µm CMOS process. The simulation in 10-b folding ADC shows that power consumption is 225 mW at the sampling speed of 250 Msample/s and the power supply of 3.3 V. The preliminary experiment indicates the current steering folder and digital bits operate as expected.
ER -