The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이 연구에서는 12캐리어 W-CDMA 애플리케이션과 같은 100G 무선 통신 시스템을 위한 0.13비트 3MS/s 1.0μm CMOS ADC에 대해 설명합니다. 제안된 ADC는 목표 해상도와 샘플링 속도에서 전력 소비와 칩 면적을 최적화하기 위해 0.13단계 파이프라인 아키텍처를 사용합니다. 입력 SHA의 영역 효율적인 게이트 부트스트랩 샘플링 스위치는 1V 공급에서도 Nyquist 속도에 대해 높은 신호 선형성을 유지합니다. SHA 및 MDAC의 8단 증폭기에서 저임피던스 피드백 경로를 사용하는 캐스코드 보상은 밀러 보상에 비해 적은 전력 소비와 면적으로 필요한 변환 속도와 위상 마진을 달성합니다. 하위 범위 지정 플래시 ADC의 로우 글리치 동적 래치는 재생성 래치 출력에서 사전 증폭기를 분리하여 비교기 입력과 관련된 반동 잡음을 줄입니다. 제안된 온칩 전류 및 전압 레퍼런스는 삼중 네거티브 TC 회로를 기반으로 합니다. 0.38 µm 0.96P12M CMOS 기술의 프로토타입 ADC는 64.5비트에서 각각 78.0LSB 및 100LSB 내에서 측정된 DNL 및 INL을 보여줍니다. ADC는 1.22MS/s에서 각각 XNUMXdB와 XNUMXdB의 최대 SNDR과 SFDR을 보여줍니다. 활성 다이 면적이 XNUMXmm인 ADC2 42.0MS/s 및 100V 공급에서 1.2mW를 소비하며 이는 0.31pJ/변환 단계의 성능 지수에 해당합니다.
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Young-Ju KIM, Kyung-Hoon LEE, Myung-Hwan LEE, Seung-Hoon LEE, "A 0.31 pJ/Conversion-Step 12-Bit 100 MS/s 0.13 µm CMOS A/D Converter for 3G Communication Systems" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 9, pp. 1194-1200, September 2009, doi: 10.1587/transele.E92.C.1194.
Abstract: This work describes a 12-bit 100 MS/s 0.13 µm CMOS ADC for 3G wireless communication systems such as two-carrier W-CDMA applications. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient gate-bootstrapped sampling switches of the input SHA maintain high signal linearity over the Nyquist rate even at a 1.0 V supply. The cascode compensation using a low-impedance feedback path in two-stage amplifiers of the SHA and MDACs achieves the required conversion speed and phase margin with less power consumption and area compared to the Miller compensation. A low-glitch dynamic latch in the sub-ranging flash ADCs reduces kickback noise referred to the input of comparator by isolating the pre-amplifier from the regeneration latch output. The proposed on-chip current and voltage references are based on triple negative TC circuits. The prototype ADC in a 0.13 µm 1P8M CMOS technology demonstrates the measured DNL and INL within 0.38LSB and 0.96LSB at 12-bit, respectively. The ADC shows a maximum SNDR and SFDR of 64.5 dB and 78.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.22 mm2 consumes 42.0 mW at 100 MS/s and a 1.2 V supply, corresponding to a figure-of-merit of 0.31 pJ/conversion-step.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1194/_p
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@ARTICLE{e92-c_9_1194,
author={Young-Ju KIM, Kyung-Hoon LEE, Myung-Hwan LEE, Seung-Hoon LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 0.31 pJ/Conversion-Step 12-Bit 100 MS/s 0.13 µm CMOS A/D Converter for 3G Communication Systems},
year={2009},
volume={E92-C},
number={9},
pages={1194-1200},
abstract={This work describes a 12-bit 100 MS/s 0.13 µm CMOS ADC for 3G wireless communication systems such as two-carrier W-CDMA applications. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient gate-bootstrapped sampling switches of the input SHA maintain high signal linearity over the Nyquist rate even at a 1.0 V supply. The cascode compensation using a low-impedance feedback path in two-stage amplifiers of the SHA and MDACs achieves the required conversion speed and phase margin with less power consumption and area compared to the Miller compensation. A low-glitch dynamic latch in the sub-ranging flash ADCs reduces kickback noise referred to the input of comparator by isolating the pre-amplifier from the regeneration latch output. The proposed on-chip current and voltage references are based on triple negative TC circuits. The prototype ADC in a 0.13 µm 1P8M CMOS technology demonstrates the measured DNL and INL within 0.38LSB and 0.96LSB at 12-bit, respectively. The ADC shows a maximum SNDR and SFDR of 64.5 dB and 78.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.22 mm2 consumes 42.0 mW at 100 MS/s and a 1.2 V supply, corresponding to a figure-of-merit of 0.31 pJ/conversion-step.},
keywords={},
doi={10.1587/transele.E92.C.1194},
ISSN={1745-1353},
month={September},}
부
TY - JOUR
TI - A 0.31 pJ/Conversion-Step 12-Bit 100 MS/s 0.13 µm CMOS A/D Converter for 3G Communication Systems
T2 - IEICE TRANSACTIONS on Electronics
SP - 1194
EP - 1200
AU - Young-Ju KIM
AU - Kyung-Hoon LEE
AU - Myung-Hwan LEE
AU - Seung-Hoon LEE
PY - 2009
DO - 10.1587/transele.E92.C.1194
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2009
AB - This work describes a 12-bit 100 MS/s 0.13 µm CMOS ADC for 3G wireless communication systems such as two-carrier W-CDMA applications. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient gate-bootstrapped sampling switches of the input SHA maintain high signal linearity over the Nyquist rate even at a 1.0 V supply. The cascode compensation using a low-impedance feedback path in two-stage amplifiers of the SHA and MDACs achieves the required conversion speed and phase margin with less power consumption and area compared to the Miller compensation. A low-glitch dynamic latch in the sub-ranging flash ADCs reduces kickback noise referred to the input of comparator by isolating the pre-amplifier from the regeneration latch output. The proposed on-chip current and voltage references are based on triple negative TC circuits. The prototype ADC in a 0.13 µm 1P8M CMOS technology demonstrates the measured DNL and INL within 0.38LSB and 0.96LSB at 12-bit, respectively. The ADC shows a maximum SNDR and SFDR of 64.5 dB and 78.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.22 mm2 consumes 42.0 mW at 100 MS/s and a 1.2 V supply, corresponding to a figure-of-merit of 0.31 pJ/conversion-step.
ER -