The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 임베디드 시스템, 마이크로프로세서, SOC 등과 같은 특정 애플리케이션의 전력 효율성을 향상시키기 위해 사전 계산 기반 콘텐츠 주소 지정 메모리(PB-CAM)의 적절한 매개변수 추출기를 합성할 수 있는 게이트 블록 선택 알고리즘을 제시합니다. 또한, 단일 비트라인을 갖는 새로운 CAM 셀 설계가 제안되었습니다. 제안된 CAM 셀 설계에는 단 하나의 고부하 비트라인만 필요하며 단지 0.35개의 트랜지스터로 구성됩니다. 전체 PB-CAM 설계는 TSMC 128μm 이중 폴리 32중 금속 CMOS 프로세스를 사용하여 Spice에서 설명되었습니다. Synopsys Nanosim을 사용하여 전력 소비를 추정했습니다. 18.21워드 x 16.75비트 CAM 크기의 실험 결과에서 제안한 PB-CAM은 PB-CAM의 적절한 매개변수 추출기를 합성하여 CAM에서 비교 연산을 1% 효과적으로 줄이고 전력 감소도 XNUMX% 절감하는 것으로 나타났습니다. XNUMX의 카운트 PB-CAM. 이는 우리가 제안한 PB-CAM이 특정 응용 분야에 더 유연하고 적응력이 있다는 것을 의미합니다.
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Shanq-Jang RUAN, Jui-Yuan HSIEH, Chia-Han LEE, "Synthesis and Design of Parameter Extractors for Low-Power Pre-Computation-Based Content-Addressable Memory" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 10, pp. 1249-1257, October 2009, doi: 10.1587/transele.E92.C.1249.
Abstract: This paper presents a gate-block selection algorithm, which can synthesize a proper parameter extractor of the pre-computation-based content-addressable memory (PB-CAM) to enhance power efficiency for specific applications such as embedded systems, microprocessor and SOC, etc. Furthermore, a novel CAM cell design with single bit-line is proposed. The proposed CAM cell design requires only one heavy loading bit-line and merely is constructed with eight transistors. The whole PB-CAM design was described in Spice with TSMC 0.35 µm double-poly quadruple-metal CMOS process. We used Synopsys Nanosim to estimate power consumption. With a 128 words by 32 bits CAM size, the experimental results showed that our proposed PB-CAM effectively reduces 18.21% of comparison operations in the CAM and saves 16.75% in power reduction by synthesizing a proper parameter extractor of the PB-CAM compared with the 1's count PB-CAM. This implies that our proposed PB-CAM is more flexible and adaptive for specific applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1249/_p
부
@ARTICLE{e92-c_10_1249,
author={Shanq-Jang RUAN, Jui-Yuan HSIEH, Chia-Han LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Synthesis and Design of Parameter Extractors for Low-Power Pre-Computation-Based Content-Addressable Memory},
year={2009},
volume={E92-C},
number={10},
pages={1249-1257},
abstract={This paper presents a gate-block selection algorithm, which can synthesize a proper parameter extractor of the pre-computation-based content-addressable memory (PB-CAM) to enhance power efficiency for specific applications such as embedded systems, microprocessor and SOC, etc. Furthermore, a novel CAM cell design with single bit-line is proposed. The proposed CAM cell design requires only one heavy loading bit-line and merely is constructed with eight transistors. The whole PB-CAM design was described in Spice with TSMC 0.35 µm double-poly quadruple-metal CMOS process. We used Synopsys Nanosim to estimate power consumption. With a 128 words by 32 bits CAM size, the experimental results showed that our proposed PB-CAM effectively reduces 18.21% of comparison operations in the CAM and saves 16.75% in power reduction by synthesizing a proper parameter extractor of the PB-CAM compared with the 1's count PB-CAM. This implies that our proposed PB-CAM is more flexible and adaptive for specific applications.},
keywords={},
doi={10.1587/transele.E92.C.1249},
ISSN={1745-1353},
month={October},}
부
TY - JOUR
TI - Synthesis and Design of Parameter Extractors for Low-Power Pre-Computation-Based Content-Addressable Memory
T2 - IEICE TRANSACTIONS on Electronics
SP - 1249
EP - 1257
AU - Shanq-Jang RUAN
AU - Jui-Yuan HSIEH
AU - Chia-Han LEE
PY - 2009
DO - 10.1587/transele.E92.C.1249
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2009
AB - This paper presents a gate-block selection algorithm, which can synthesize a proper parameter extractor of the pre-computation-based content-addressable memory (PB-CAM) to enhance power efficiency for specific applications such as embedded systems, microprocessor and SOC, etc. Furthermore, a novel CAM cell design with single bit-line is proposed. The proposed CAM cell design requires only one heavy loading bit-line and merely is constructed with eight transistors. The whole PB-CAM design was described in Spice with TSMC 0.35 µm double-poly quadruple-metal CMOS process. We used Synopsys Nanosim to estimate power consumption. With a 128 words by 32 bits CAM size, the experimental results showed that our proposed PB-CAM effectively reduces 18.21% of comparison operations in the CAM and saves 16.75% in power reduction by synthesizing a proper parameter extractor of the PB-CAM compared with the 1's count PB-CAM. This implies that our proposed PB-CAM is more flexible and adaptive for specific applications.
ER -