The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
다양한 프로세서 아키텍처 전반에 걸쳐 Java 워크로드가 널리 보급되어 있음에도 불구하고 다양한 프로세서 설계 결정이 Java 성능에 미치는 영향에 대해 게시된 데이터는 거의 없습니다. 우리는 최신 수퍼스칼라 프로세서의 복잡성과 가상 머신을 사용하여 Java 바이트코드를 실행하는 것과 관련된 추가적인 복잡성으로 인해 발생하는 대규모 설계 공간에 데이터 부족이 있다고 생각합니다. 이러한 단점을 해결하기 위해 우리는 통계적으로 엄격한 방법론을 사용하여 다양한 프로세서 마이크로아키텍처 매개변수가 Java 실행 성능에 미치는 영향을 체계적으로 정량화합니다. 채택된 방법론을 사용하면 벤치마크 애플리케이션당 단 35개의 관찰을 사용하여 32개 요인(72억 개의 잠재적 구성)으로 구성된 대규모 설계 공간에서 중요한 요인 효과를 효율적으로 스크리닝할 수 있습니다. 우리는 35개 벤치마크 애플리케이션에 대한 13개 요소 각각의 중요성을 정량화하고 표로 작성합니다. 이러한 표는 Java 성능에 대한 다양한 통찰력을 제공하는 동시에 명령 전달 메커니즘, 특히 명령 캐시 및 ITLB 설계 매개변수의 성능 중요성을 지속적으로 강조합니다. 또한 이러한 테이블을 통해 설계자는 다양한 설계 결정의 상대적 영향에 대한 추정치를 제공함으로써 Java 작업 부하에 대한 프로세서 병목 현상을 식별할 수 있습니다.
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Pradeep RAO, Kazuaki MURAKAMI, "Identifying Processor Bottlenecks in Virtual Machine Based Execution of Java Bytecode" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 10, pp. 1265-1275, October 2009, doi: 10.1587/transele.E92.C.1265.
Abstract: Despite the prevalence of Java workloads across a variety of processor architectures, there is very little published data on the impact of the various processor design decisions on Java performance. We attribute the lack of data to the large design space resulting from the complexity of the modern superscalar processor and the additional complexities associated with executing Java bytecode using a virtual machine. To address this shortcoming, we use a statistically rigorous methodology to systematically quantify the the impact of the various processor microarchitecture parameters on Java execution performance. The adopted methodology enables efficient screening of significant factor effects in a large design space consisting of 35 factors (32-billion potential configurations) using merely 72 observations per benchmark application. We quantify and tabulate the significance of each of the 35 factors for 13 benchmark applications. While these tables provide various insights into Java performance, they consistently highlight the performance significance of the instruction delivery mechanism, especially the instruction cache and the ITLB design parameters. Furthermore, these tables enable the architect to identify processor bottlenecks for Java workloads by providing an estimate of the relative impact of various design decisions.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1265/_p
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@ARTICLE{e92-c_10_1265,
author={Pradeep RAO, Kazuaki MURAKAMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Identifying Processor Bottlenecks in Virtual Machine Based Execution of Java Bytecode},
year={2009},
volume={E92-C},
number={10},
pages={1265-1275},
abstract={Despite the prevalence of Java workloads across a variety of processor architectures, there is very little published data on the impact of the various processor design decisions on Java performance. We attribute the lack of data to the large design space resulting from the complexity of the modern superscalar processor and the additional complexities associated with executing Java bytecode using a virtual machine. To address this shortcoming, we use a statistically rigorous methodology to systematically quantify the the impact of the various processor microarchitecture parameters on Java execution performance. The adopted methodology enables efficient screening of significant factor effects in a large design space consisting of 35 factors (32-billion potential configurations) using merely 72 observations per benchmark application. We quantify and tabulate the significance of each of the 35 factors for 13 benchmark applications. While these tables provide various insights into Java performance, they consistently highlight the performance significance of the instruction delivery mechanism, especially the instruction cache and the ITLB design parameters. Furthermore, these tables enable the architect to identify processor bottlenecks for Java workloads by providing an estimate of the relative impact of various design decisions.},
keywords={},
doi={10.1587/transele.E92.C.1265},
ISSN={1745-1353},
month={October},}
부
TY - JOUR
TI - Identifying Processor Bottlenecks in Virtual Machine Based Execution of Java Bytecode
T2 - IEICE TRANSACTIONS on Electronics
SP - 1265
EP - 1275
AU - Pradeep RAO
AU - Kazuaki MURAKAMI
PY - 2009
DO - 10.1587/transele.E92.C.1265
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2009
AB - Despite the prevalence of Java workloads across a variety of processor architectures, there is very little published data on the impact of the various processor design decisions on Java performance. We attribute the lack of data to the large design space resulting from the complexity of the modern superscalar processor and the additional complexities associated with executing Java bytecode using a virtual machine. To address this shortcoming, we use a statistically rigorous methodology to systematically quantify the the impact of the various processor microarchitecture parameters on Java execution performance. The adopted methodology enables efficient screening of significant factor effects in a large design space consisting of 35 factors (32-billion potential configurations) using merely 72 observations per benchmark application. We quantify and tabulate the significance of each of the 35 factors for 13 benchmark applications. While these tables provide various insights into Java performance, they consistently highlight the performance significance of the instruction delivery mechanism, especially the instruction cache and the ITLB design parameters. Furthermore, these tables enable the architect to identify processor bottlenecks for Java workloads by providing an estimate of the relative impact of various design decisions.
ER -