The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
일반 모바일 기기, 자동차 가전, 파워 IC, 디스플레이 IC, CMOS 이미지 센서 등의 마이크로 컨트롤 유닛(MCU)에 유용한 비동기 멀티비트 OTP(One-Time Programmable) 메모리를 설계했습니다. 기존 OTP 셀은 액세스 트랜지스터, 안티퓨즈 역할을 하는 NMOS 커패시터, 셀당 단일 비트를 저장하는 정전기 방전(ESD) 보호를 위한 게이트 접지 NMOS 다이오드로 구성됩니다. 이에 반해 새롭게 제안된 OTP 셀은 PMOS 프로그램 트랜지스터, NMOS 읽기 트랜지스터, n 안티퓨즈로서의 NMOS 커패시터, 및 n 저장할 안티퓨즈를 선택하는 NMOS 스위치 n 셀당 비트. 우리는 로직 공급 전압 VDD(=1.5V)와 외부 프로그램 전압 VPPE(=8.5V)를 사용했습니다. 또한 기존의 전류 감지 증폭기[3] 대신 클럭 인버터 방식의 감지 증폭기[2]를 사용하여 감지 증폭기 회로를 단순화하였다. 128바이트의 비동기 멀티비트 OTP는 매그나칩 0.13μm CMOS 공정으로 설계됐다. 레이아웃 영역은 229.52입니다.
Chul-Ho CHOI
Jae-Hyung LEE
Tae-Hoon KIM
Oe-Yong SHIM
Yoon-Geum HWANG
Kwang-Seon AHN
Pan-Bong HA
Young-Hee KIM
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Chul-Ho CHOI, Jae-Hyung LEE, Tae-Hoon KIM, Oe-Yong SHIM, Yoon-Geum HWANG, Kwang-Seon AHN, Pan-Bong HA, Young-Hee KIM, "Design of Asynchronous Multi-Bit OTP Memory" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 1, pp. 173-177, January 2009, doi: 10.1587/transele.E92.C.173.
Abstract: We designed an asynchronous multi-bit one-time-programmable (OTP) memory which is useful for micro control units (MCUs) of general mobile devices, automobile appliances, power ICs, display ICs, and CMOS image sensors. A conventional OTP cell consists of an access transistor, a NMOS capacitor as antifuse, and a gate-grounded NMOS diode for electrostatic discharge (ESD) protection to store a single bit per cell. On the contrary, a newly proposed OTP cell consists of a PMOS program transistor, a NMOS read transistor, n NMOS capacitors as antifuses, and n NMOS switches selecting antifuse to store n bits per cell. We used logic supply voltage VDD (=1.5 V) and an external program voltage VPPE (=8.5 V). Also, we simplified the sens amplifier circuit by using the sense amplifier of clocked inverter type [3] instead of the conventional current sens amplifier [2]. The asynchronous multi-bit OTP of 128 bytes is designed with Magnachip 0.13 µm CMOS process. The layout area is 229.52
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.173/_p
부
@ARTICLE{e92-c_1_173,
author={Chul-Ho CHOI, Jae-Hyung LEE, Tae-Hoon KIM, Oe-Yong SHIM, Yoon-Geum HWANG, Kwang-Seon AHN, Pan-Bong HA, Young-Hee KIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of Asynchronous Multi-Bit OTP Memory},
year={2009},
volume={E92-C},
number={1},
pages={173-177},
abstract={We designed an asynchronous multi-bit one-time-programmable (OTP) memory which is useful for micro control units (MCUs) of general mobile devices, automobile appliances, power ICs, display ICs, and CMOS image sensors. A conventional OTP cell consists of an access transistor, a NMOS capacitor as antifuse, and a gate-grounded NMOS diode for electrostatic discharge (ESD) protection to store a single bit per cell. On the contrary, a newly proposed OTP cell consists of a PMOS program transistor, a NMOS read transistor, n NMOS capacitors as antifuses, and n NMOS switches selecting antifuse to store n bits per cell. We used logic supply voltage VDD (=1.5 V) and an external program voltage VPPE (=8.5 V). Also, we simplified the sens amplifier circuit by using the sense amplifier of clocked inverter type [3] instead of the conventional current sens amplifier [2]. The asynchronous multi-bit OTP of 128 bytes is designed with Magnachip 0.13 µm CMOS process. The layout area is 229.52
keywords={},
doi={10.1587/transele.E92.C.173},
ISSN={1745-1353},
month={January},}
부
TY - JOUR
TI - Design of Asynchronous Multi-Bit OTP Memory
T2 - IEICE TRANSACTIONS on Electronics
SP - 173
EP - 177
AU - Chul-Ho CHOI
AU - Jae-Hyung LEE
AU - Tae-Hoon KIM
AU - Oe-Yong SHIM
AU - Yoon-Geum HWANG
AU - Kwang-Seon AHN
AU - Pan-Bong HA
AU - Young-Hee KIM
PY - 2009
DO - 10.1587/transele.E92.C.173
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2009
AB - We designed an asynchronous multi-bit one-time-programmable (OTP) memory which is useful for micro control units (MCUs) of general mobile devices, automobile appliances, power ICs, display ICs, and CMOS image sensors. A conventional OTP cell consists of an access transistor, a NMOS capacitor as antifuse, and a gate-grounded NMOS diode for electrostatic discharge (ESD) protection to store a single bit per cell. On the contrary, a newly proposed OTP cell consists of a PMOS program transistor, a NMOS read transistor, n NMOS capacitors as antifuses, and n NMOS switches selecting antifuse to store n bits per cell. We used logic supply voltage VDD (=1.5 V) and an external program voltage VPPE (=8.5 V). Also, we simplified the sens amplifier circuit by using the sense amplifier of clocked inverter type [3] instead of the conventional current sens amplifier [2]. The asynchronous multi-bit OTP of 128 bytes is designed with Magnachip 0.13 µm CMOS process. The layout area is 229.52
ER -