The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
조회수
104
본 논문에서는 플래시 아날로그-디지털 변환기(ADC)에서 프리앰프 어레이의 전력 소비를 추정하기 위해 저항 평균 네트워크와 보간 기법을 조사하고 분석합니다. 플래시 ADC 설계자는 다양한 구성의 상대적인 전력 소비를 비교함으로써 플래시 ADC의 작동 속도와 분해능이 지정될 때 가장 전력 효율적인 아키텍처를 선택할 수 있습니다. 정량적 분석을 기반으로 5μm CMOS 프로세스로 소형 0.13비트 플래시 ADC를 설계하고 제작했습니다. 제안된 ADC는 180V 전원에서 1.2mW를 소비하고 0.16mm를 차지한다.2 활동 영역. 3.2GS/s에서 작동하는 ENOB는 4.44비트 및 ERBW 1.65GHz입니다. 4.2GS/s에서 ENOB는 4.20비트이고 ERBW는 1.75GHz입니다. 이 ADC는 각각 2.59 및 2.80 GS/s에서 3.2 및 4.2 pJ/전환 단계의 FOM을 달성합니다.
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부
Ying-Zu LIN, Soon-Jyh CHANG, Yen-Ting LIU, "A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 2, pp. 258-268, February 2009, doi: 10.1587/transele.E92.C.258.
Abstract: This paper investigates and analyzes the resistive averaging network and interpolation technique to estimate the power consumption of preamplifier arrays in a flash analog-to-digital converter (ADC). By comparing the relative power consumption of various configurations, flash ADC designers can select the most power efficient architecture when the operation speed and resolution of a flash ADC are specified. Based on the quantitative analysis, a compact 5-bit flash ADC is designed and fabricated in a 0.13-µm CMOS process. The proposed ADC consumes 180 mW from a 1.2-V supply and occupies 0.16-mm2 active area. Operating at 3.2 GS/s, the ENOB is 4.44 bit and ERBW 1.65 GHz. At 4.2 GS/s, the ENOB is 4.20 bit and ERBW 1.75 GHz. This ADC achieves FOMs of 2.59 and 2.80 pJ/conversion-step at 3.2 and 4.2 GS/s, respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.258/_p
부
@ARTICLE{e92-c_2_258,
author={Ying-Zu LIN, Soon-Jyh CHANG, Yen-Ting LIU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process},
year={2009},
volume={E92-C},
number={2},
pages={258-268},
abstract={This paper investigates and analyzes the resistive averaging network and interpolation technique to estimate the power consumption of preamplifier arrays in a flash analog-to-digital converter (ADC). By comparing the relative power consumption of various configurations, flash ADC designers can select the most power efficient architecture when the operation speed and resolution of a flash ADC are specified. Based on the quantitative analysis, a compact 5-bit flash ADC is designed and fabricated in a 0.13-µm CMOS process. The proposed ADC consumes 180 mW from a 1.2-V supply and occupies 0.16-mm2 active area. Operating at 3.2 GS/s, the ENOB is 4.44 bit and ERBW 1.65 GHz. At 4.2 GS/s, the ENOB is 4.20 bit and ERBW 1.75 GHz. This ADC achieves FOMs of 2.59 and 2.80 pJ/conversion-step at 3.2 and 4.2 GS/s, respectively.},
keywords={},
doi={10.1587/transele.E92.C.258},
ISSN={1745-1353},
month={February},}
부
TY - JOUR
TI - A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process
T2 - IEICE TRANSACTIONS on Electronics
SP - 258
EP - 268
AU - Ying-Zu LIN
AU - Soon-Jyh CHANG
AU - Yen-Ting LIU
PY - 2009
DO - 10.1587/transele.E92.C.258
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2009
AB - This paper investigates and analyzes the resistive averaging network and interpolation technique to estimate the power consumption of preamplifier arrays in a flash analog-to-digital converter (ADC). By comparing the relative power consumption of various configurations, flash ADC designers can select the most power efficient architecture when the operation speed and resolution of a flash ADC are specified. Based on the quantitative analysis, a compact 5-bit flash ADC is designed and fabricated in a 0.13-µm CMOS process. The proposed ADC consumes 180 mW from a 1.2-V supply and occupies 0.16-mm2 active area. Operating at 3.2 GS/s, the ENOB is 4.44 bit and ERBW 1.65 GHz. At 4.2 GS/s, the ENOB is 4.20 bit and ERBW 1.75 GHz. This ADC achieves FOMs of 2.59 and 2.80 pJ/conversion-step at 3.2 and 4.2 GS/s, respectively.
ER -