The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
무선 주파수(RF) 집적 회로(IC)를 위한 온칩 ESD 보호 설계를 위한 임피던스 절연 기술이 제안되었으며, 이는 두꺼운 상부 금속을 사용하는 0.25μm CMOS 프로세스에서 성공적으로 검증되었습니다. RF 회로의 작동 주파수에서 LC 탱크의 공진을 통해 ESD 보호 장치의 임피던스(특히 기생 용량)가 저잡음 증폭기(LNA)의 RF 입력 노드에서 분리될 수 있습니다. 따라서 LNA는 제안된 임피던스 절연 기술과 함께 설계되어 우수한 RF 성능과 높은 ESD 견고성을 동시에 달성할 수 있습니다. 전력 이득(S21제안된 임피던스 절연 기법을 적용한 ESD 보호 회로의 잡음 지수와 잡음 지수를 실험적으로 측정하고 기존 이중 다이오드 ESD 보호 방식과 비교하였다. 제안된 임피던스 절연 기술은 RF IC의 온칩 ESD 보호 설계에 적합한 것으로 입증되었습니다.
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부
Ming-Dou KER, Yuan-Wen HSIAO, "Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 3, pp. 341-351, March 2009, doi: 10.1587/transele.E92.C.341.
Abstract: An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-µm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore, the LNA can be co-designed with the proposed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S21-parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation technique have been experimentally measured and compared to those with the conventional double-diodes ESD protection scheme. The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.341/_p
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@ARTICLE{e92-c_3_341,
author={Ming-Dou KER, Yuan-Wen HSIAO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits},
year={2009},
volume={E92-C},
number={3},
pages={341-351},
abstract={An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-µm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore, the LNA can be co-designed with the proposed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S21-parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation technique have been experimentally measured and compared to those with the conventional double-diodes ESD protection scheme. The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs.},
keywords={},
doi={10.1587/transele.E92.C.341},
ISSN={1745-1353},
month={March},}
부
TY - JOUR
TI - Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 341
EP - 351
AU - Ming-Dou KER
AU - Yuan-Wen HSIAO
PY - 2009
DO - 10.1587/transele.E92.C.341
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2009
AB - An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-µm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore, the LNA can be co-designed with the proposed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S21-parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation technique have been experimentally measured and compared to those with the conventional double-diodes ESD protection scheme. The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs.
ER -