The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
메모리 설계에서는 더 작은 크기와 낮은 전력이 문제입니다. ROM에서 사용되는 전력의 대부분은 주소라인, 워드라인, 비트라인, 디코더 등의 라인 커패시턴스에서 소모된다. 본 논문에서는 전력 소모 및 칩 면적 감소를 위해 비트라인의 기생 커패시턴스와 행 디코더의 면적을 줄이기 위한 새로운 HG(Half Grouping) 압축 방식의 ROM 설계를 제시한다. 512 포인트 FFT 블록의 ROM 설계 결과, 제안하는 방법이 기존 방법에 비해 면적은 40.6%, 전력은 42.12%, 트랜지스터 개수는 37.82% 감소하는 것을 알 수 있다. 제안된 방법으로 설계된 ROM은 0.35 µm CMOS 공정으로 구현된다. 단일 5.8V 전원 공급 장치로 100MHz에서 3.3mW를 소비합니다.
Ki-Sang JUNG
Kang-Jik KIM
Young-Eun KIM
Jin-Gyun CHUNG
Ki-Hyun PYUN
Jong-Yeol LEE
Hang-Geun JEONG
Seong-Ik CHO
ROM과, HG(하프 그룹화), 기억
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부
Ki-Sang JUNG, Kang-Jik KIM, Young-Eun KIM, Jin-Gyun CHUNG, Ki-Hyun PYUN, Jong-Yeol LEE, Hang-Geun JEONG, Seong-Ik CHO, "The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 3, pp. 352-355, March 2009, doi: 10.1587/transele.E92.C.352.
Abstract: In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35 µm CMOS process. It consumes 5.8 mW at 100 MHz with a single 3.3 V power supply.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.352/_p
부
@ARTICLE{e92-c_3_352,
author={Ki-Sang JUNG, Kang-Jik KIM, Young-Eun KIM, Jin-Gyun CHUNG, Ki-Hyun PYUN, Jong-Yeol LEE, Hang-Geun JEONG, Seong-Ik CHO, },
journal={IEICE TRANSACTIONS on Electronics},
title={The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction},
year={2009},
volume={E92-C},
number={3},
pages={352-355},
abstract={In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35 µm CMOS process. It consumes 5.8 mW at 100 MHz with a single 3.3 V power supply.},
keywords={},
doi={10.1587/transele.E92.C.352},
ISSN={1745-1353},
month={March},}
부
TY - JOUR
TI - The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction
T2 - IEICE TRANSACTIONS on Electronics
SP - 352
EP - 355
AU - Ki-Sang JUNG
AU - Kang-Jik KIM
AU - Young-Eun KIM
AU - Jin-Gyun CHUNG
AU - Ki-Hyun PYUN
AU - Jong-Yeol LEE
AU - Hang-Geun JEONG
AU - Seong-Ik CHO
PY - 2009
DO - 10.1587/transele.E92.C.352
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2009
AB - In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35 µm CMOS process. It consumes 5.8 mW at 100 MHz with a single 3.3 V power supply.
ER -