The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
CMOS 디지털 통합의 논리 연산은 전원 공급 장치(PS) 강하량이 오류 임계값에 가까워짐에 따라 실패할 가능성이 매우 높습니다. PS 전압 변동은 32nm CMOS 기술의 90비트 마이크로프로세서에 내장된 노이즈 모니터를 특징으로 하며 논리적 오류 분석을 위한 명령 수준 프로그래밍을 통해 작동 오류와 관련됩니다. 전압 강하 크기와 활성화된 논리 경로의 조합에 따라 오류 민감도와 오류 등급이 결정됩니다. PS 노이즈가 디지털 집적 회로의 논리적 작동에 미치는 영향을 자세히 이해하기 위해 실험적 관찰과 단순화된 시뮬레이션이 적용됩니다.
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Mitsuya FUKAZAWA, Masanori KURIMOTO, Rei AKIYAMA, Hidehiro TAKATA, Makoto NAGATA, "Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 475-482, April 2009, doi: 10.1587/transele.E92.C.475.
Abstract: Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.475/_p
부
@ARTICLE{e92-c_4_475,
author={Mitsuya FUKAZAWA, Masanori KURIMOTO, Rei AKIYAMA, Hidehiro TAKATA, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations},
year={2009},
volume={E92-C},
number={4},
pages={475-482},
abstract={Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.},
keywords={},
doi={10.1587/transele.E92.C.475},
ISSN={1745-1353},
month={April},}
부
TY - JOUR
TI - Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations
T2 - IEICE TRANSACTIONS on Electronics
SP - 475
EP - 482
AU - Mitsuya FUKAZAWA
AU - Masanori KURIMOTO
AU - Rei AKIYAMA
AU - Hidehiro TAKATA
AU - Makoto NAGATA
PY - 2009
DO - 10.1587/transele.E92.C.475
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.
ER -