The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
이 편지에서는 면적 효율적인 LC-VCO를 사용하는 초저지터 클록 생성기를 소개합니다. 온칩 인덕터의 면적을 최대한 활용하기 위해 PLL(위상 고정 루프)의 루프 필터가 인덕터 아래에 위치합니다. 0.13 µm CMOS 프로세스로 구현된 프로토타입 칩은 105 MHz ~ 225 MHz의 클록 주파수를 달성하는 동시에 4.2 V 공급 장치에서 1.2 mW를 소비합니다. 제안된 클럭 발생기의 측정된 rms 지터와 정규화된 rms 지터는 2.8MHz에서 각각 0.031ps와 105%입니다.
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부
Joonhee LEE, Sungjun KIM, Sehyung JEON, Woojae LEE, SeongHwan CHO, "A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-µm CMOS" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 589-591, April 2009, doi: 10.1587/transele.E92.C.589.
Abstract: This letter presents an ultra low-jitter clock generator that employs an area-efficient LC-VCO. In order to fully utilize the area of the on-chip inductor, the loop filter of a phase locked loop (PLL) is located underneath the inductor. A prototype chip implemented in 0.13 µm CMOS process achieves 105 MHz to 225 MHz of clock frequency while consuming 4.2 mW from 1.2 V supply. The measured rms jitter and normalized rms jitter of the proposed clock generator are 2.8 ps and 0.031% at 105 MHz, respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.589/_p
부
@ARTICLE{e92-c_4_589,
author={Joonhee LEE, Sungjun KIM, Sehyung JEON, Woojae LEE, SeongHwan CHO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-µm CMOS},
year={2009},
volume={E92-C},
number={4},
pages={589-591},
abstract={This letter presents an ultra low-jitter clock generator that employs an area-efficient LC-VCO. In order to fully utilize the area of the on-chip inductor, the loop filter of a phase locked loop (PLL) is located underneath the inductor. A prototype chip implemented in 0.13 µm CMOS process achieves 105 MHz to 225 MHz of clock frequency while consuming 4.2 mW from 1.2 V supply. The measured rms jitter and normalized rms jitter of the proposed clock generator are 2.8 ps and 0.031% at 105 MHz, respectively.},
keywords={},
doi={10.1587/transele.E92.C.589},
ISSN={1745-1353},
month={April},}
부
TY - JOUR
TI - A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-µm CMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 589
EP - 591
AU - Joonhee LEE
AU - Sungjun KIM
AU - Sehyung JEON
AU - Woojae LEE
AU - SeongHwan CHO
PY - 2009
DO - 10.1587/transele.E92.C.589
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - This letter presents an ultra low-jitter clock generator that employs an area-efficient LC-VCO. In order to fully utilize the area of the on-chip inductor, the loop filter of a phase locked loop (PLL) is located underneath the inductor. A prototype chip implemented in 0.13 µm CMOS process achieves 105 MHz to 225 MHz of clock frequency while consuming 4.2 mW from 1.2 V supply. The measured rms jitter and normalized rms jitter of the proposed clock generator are 2.8 ps and 0.031% at 105 MHz, respectively.
ER -