The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 10nm 이하 수직형 MOSFET의 소자 성능을 조사한다. 기존 평면형 MOSFET의 단점 중 하나는 10nm 이하 세대에서는 단채널 효과로 인해 차단 누설 전류가 증가하지만, 더욱이 서브-20nm와 같은 양자역학적 구속 효과로 인해 구동 전류가 감소한다는 점입니다. 밴드효과와 반전층의 고갈. 실리콘 기둥 직경을 4nm에서 2nm로 축소함으로써 수직 MOSFET은 풋프린트당 구동 전류를 약 1배로 늘리고 풋프린트당 총 컷오프 누설 전류를 60/10 미만으로 억제하는 것으로 처음으로 나타났습니다. 동시. 또한, 이러한 수직 MOSFET 성능 향상의 메커니즘이 명확해졌습니다. 이 연구의 결과는 수직 MOSFET이 기존 평면 MOSFET의 단점을 극복하고 XNUMXnm 이하 세대를 통해 높은 장치 성능을 달성할 수 있음을 보여줍니다.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Tetsuo ENDOH, Yuto NORIFUSA, "Scalability of Vertical MOSFETs in Sub-10 nm Generation and Its Mechanism" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 5, pp. 594-597, May 2009, doi: 10.1587/transele.E92.C.594.
Abstract: In this paper, the device performances of sub-10 nm Vertical MOSFETs are investigated. One of the drawbacks of conventional planar MOSFETs is that in the sub-10 nm generation, its cutoff leakage current increases due to the short channel effects, but even more, its driving current decreases due to the quantum mechanical confinement effects such as the sub-band effect and the depletion of the inversion layer. It is shown for the first time that by downscaling the silicon pillar diameter from 20 nm to 4 nm, the Vertical MOSFET increases its driving current per footprint to about 2 times and suppresses its total cutoff leakage current per footprint to less than 1/60 at the same time. Moreover, the mechanisms of these improvements of Vertical MOSFET performances are clarified. The results of this work show that Vertical MOSFETs can overcome the drawbacks of conventional planar MOSFETs and achieve the high device performance through the sub-10 nm generation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.594/_p
부
@ARTICLE{e92-c_5_594,
author={Tetsuo ENDOH, Yuto NORIFUSA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Scalability of Vertical MOSFETs in Sub-10 nm Generation and Its Mechanism},
year={2009},
volume={E92-C},
number={5},
pages={594-597},
abstract={In this paper, the device performances of sub-10 nm Vertical MOSFETs are investigated. One of the drawbacks of conventional planar MOSFETs is that in the sub-10 nm generation, its cutoff leakage current increases due to the short channel effects, but even more, its driving current decreases due to the quantum mechanical confinement effects such as the sub-band effect and the depletion of the inversion layer. It is shown for the first time that by downscaling the silicon pillar diameter from 20 nm to 4 nm, the Vertical MOSFET increases its driving current per footprint to about 2 times and suppresses its total cutoff leakage current per footprint to less than 1/60 at the same time. Moreover, the mechanisms of these improvements of Vertical MOSFET performances are clarified. The results of this work show that Vertical MOSFETs can overcome the drawbacks of conventional planar MOSFETs and achieve the high device performance through the sub-10 nm generation.},
keywords={},
doi={10.1587/transele.E92.C.594},
ISSN={1745-1353},
month={May},}
부
TY - JOUR
TI - Scalability of Vertical MOSFETs in Sub-10 nm Generation and Its Mechanism
T2 - IEICE TRANSACTIONS on Electronics
SP - 594
EP - 597
AU - Tetsuo ENDOH
AU - Yuto NORIFUSA
PY - 2009
DO - 10.1587/transele.E92.C.594
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2009
AB - In this paper, the device performances of sub-10 nm Vertical MOSFETs are investigated. One of the drawbacks of conventional planar MOSFETs is that in the sub-10 nm generation, its cutoff leakage current increases due to the short channel effects, but even more, its driving current decreases due to the quantum mechanical confinement effects such as the sub-band effect and the depletion of the inversion layer. It is shown for the first time that by downscaling the silicon pillar diameter from 20 nm to 4 nm, the Vertical MOSFET increases its driving current per footprint to about 2 times and suppresses its total cutoff leakage current per footprint to less than 1/60 at the same time. Moreover, the mechanisms of these improvements of Vertical MOSFET performances are clarified. The results of this work show that Vertical MOSFETs can overcome the drawbacks of conventional planar MOSFETs and achieve the high device performance through the sub-10 nm generation.
ER -