The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
우리는 3차원 계단형 NAND 플래시 메모리를 제안합니다. 수직형 채널이 있어 1층에서도 충분히 긴 채널 연출이 가능합니다.2 크기. 그리고 3개의 계단으로 채널이 수직으로 연결된 3차원 구조를 가지고 있습니다. 따라서 실리콘 적층 공정 없이 적층 어레이 구조와 같은 고밀도를 얻을 수 있다. XNUMXF로 낸드플래시 메모리를 만들 수 있다2 셀 크기. SILVACO ATLAS 시뮬레이션을 사용하여 프로그램, 삭제, 읽기 등의 계단식 NAND 플래시 메모리 특성을 연구합니다. 또한, 그 제조방법을 제안한다.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Yoon KIM, Seongjae CHO, Gil Sung LEE, Il Han PARK, Jong Duk LEE, Hyungcheol SHIN, Byung-Gook PARK, "3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 5, pp. 653-658, May 2009, doi: 10.1587/transele.E92.C.653.
Abstract: We propose a 3-dimensional terraced NAND flash memory. It has a vertical channel so it is possible to make a long enough channel in 1F2 size. And it has 3-dimensional structure whose channel is connected vertically along with two stairs. So we can obtain high density as in the stacked array structure, without silicon stacking process. We can make NAND flash memory with 3F2 cell size. Using SILVACO ATLAS simulation, we study terraced NAND flash memory characteristics such as program, erase, and read. Also, its fabrication method is proposed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.653/_p
부
@ARTICLE{e92-c_5_653,
author={Yoon KIM, Seongjae CHO, Gil Sung LEE, Il Han PARK, Jong Duk LEE, Hyungcheol SHIN, Byung-Gook PARK, },
journal={IEICE TRANSACTIONS on Electronics},
title={3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array},
year={2009},
volume={E92-C},
number={5},
pages={653-658},
abstract={We propose a 3-dimensional terraced NAND flash memory. It has a vertical channel so it is possible to make a long enough channel in 1F2 size. And it has 3-dimensional structure whose channel is connected vertically along with two stairs. So we can obtain high density as in the stacked array structure, without silicon stacking process. We can make NAND flash memory with 3F2 cell size. Using SILVACO ATLAS simulation, we study terraced NAND flash memory characteristics such as program, erase, and read. Also, its fabrication method is proposed.},
keywords={},
doi={10.1587/transele.E92.C.653},
ISSN={1745-1353},
month={May},}
부
TY - JOUR
TI - 3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
T2 - IEICE TRANSACTIONS on Electronics
SP - 653
EP - 658
AU - Yoon KIM
AU - Seongjae CHO
AU - Gil Sung LEE
AU - Il Han PARK
AU - Jong Duk LEE
AU - Hyungcheol SHIN
AU - Byung-Gook PARK
PY - 2009
DO - 10.1587/transele.E92.C.653
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2009
AB - We propose a 3-dimensional terraced NAND flash memory. It has a vertical channel so it is possible to make a long enough channel in 1F2 size. And it has 3-dimensional structure whose channel is connected vertically along with two stairs. So we can obtain high density as in the stacked array structure, without silicon stacking process. We can make NAND flash memory with 3F2 cell size. Using SILVACO ATLAS simulation, we study terraced NAND flash memory characteristics such as program, erase, and read. Also, its fabrication method is proposed.
ER -