The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
인덕터가 없는 프리스케일러가 있는 60GHz 위상 고정 루프(PLL)는 90nm CMOS 프로세스로 제작됩니다. 인덕터가 없는 프리스케일러는 이전에 보고된 것보다 칩 면적이 더 작습니다. PLL은 61~63GHz에서 작동하고 78V 공급 장치에서 1.2mW를 소비합니다. 반송파로부터 오프셋된 100kHz 및 1MHz에서의 위상 잡음은 각각 -72 및 -80dBc/Hz입니다. 프리스케일러는 80을 차지합니다.
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Hiroaki HOSHINO, Ryoichi TACHIBANA, Toshiya MITOMO, Naoko ONO, Yoshiaki YOSHIHARA, Ryuichi FUJIMOTO, "A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 6, pp. 785-791, June 2009, doi: 10.1587/transele.E92.C.785.
Abstract: A 60-GHz phase-locked loop (PLL) with an inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 80
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.785/_p
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@ARTICLE{e92-c_6_785,
author={Hiroaki HOSHINO, Ryoichi TACHIBANA, Toshiya MITOMO, Naoko ONO, Yoshiaki YOSHIHARA, Ryuichi FUJIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS},
year={2009},
volume={E92-C},
number={6},
pages={785-791},
abstract={A 60-GHz phase-locked loop (PLL) with an inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 80
keywords={},
doi={10.1587/transele.E92.C.785},
ISSN={1745-1353},
month={June},}
부
TY - JOUR
TI - A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 785
EP - 791
AU - Hiroaki HOSHINO
AU - Ryoichi TACHIBANA
AU - Toshiya MITOMO
AU - Naoko ONO
AU - Yoshiaki YOSHIHARA
AU - Ryuichi FUJIMOTO
PY - 2009
DO - 10.1587/transele.E92.C.785
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2009
AB - A 60-GHz phase-locked loop (PLL) with an inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 80
ER -