The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
TI(Time-interleaved) ADC(아날로그-디지털 변환기)는 초광대역, 고속 직렬 링크, 초광대역, 인지 라디오와 소프트웨어 정의 라디오. 그러나 채널 불일치(대역폭, 오프셋, 이득 및 타이밍)로 인한 여러 왜곡 소스의 결합된 효과는 시스템 성능과 TI ADC의 전력 소비에 심각한 영향을 미치므로 초기 설계 단계부터 이를 고려해야 합니다. 본 문서에서는 플랫폼 기반 방법론을 통해 TI ADC의 시스템 수준 설계를 다루므로 다양한 속도/분해능 시나리오는 물론 병렬성이 정확도, 수율, 샘플링 속도, 면적 및 전력 소비에 미치는 영향을 효과적으로 조사할 수 있습니다. TI 연속 근사 ADC의 설계 공간 탐색은 몬테카를로 시뮬레이션을 통해 하향식으로 수행됩니다. 이는 90nm 1V CMOS 프로세스에서 주요 빌딩 블록의 실행 가능한 구현을 특성화한 후 상향식으로 구축된 동작 모델을 활용하는 것입니다. 결과적으로 0.15pJ/변환 단계 미만의 뛰어난 성능 지수를 제공할 수 있는 TI ADC의 두 가지 구현이 제안되었습니다.
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Sergio SAPONARA, Pierluigi NUZZO, Claudio NANI, Geert VAN DER PLAS, Luca FANUCCI, "Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 6, pp. 843-851, June 2009, doi: 10.1587/transele.E92.C.843.
Abstract: Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-efficient solution to realize the high sampling rates required in single-chip transceivers for the emerging communication schemes: ultra-wideband, fast serial links, cognitive-radio and software-defined radio. However, the combined effects of multiple distortion sources due to channel mismatches (bandwidth, offset, gain and timing) severely affect system performance and power consumption of a TI ADC and need to be accounted for since the earlier design phases. In this paper, system-level design of TI ADCs is addressed through a platform-based methodology, enabling effective investigation of different speed/resolution scenarios as well as the impact of parallelism on accuracy, yield, sampling-rate, area and power consumption. Design space exploration of a TI successive approximation ADC is performed top-down via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing feasible implementations of the main building blocks in a 90-nm 1-V CMOS process. As a result, two implementations of the TI ADC are proposed that are capable to provide an outstanding figure-of-merit below 0.15 pJ/conversion-step.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.843/_p
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@ARTICLE{e92-c_6_843,
author={Sergio SAPONARA, Pierluigi NUZZO, Claudio NANI, Geert VAN DER PLAS, Luca FANUCCI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters},
year={2009},
volume={E92-C},
number={6},
pages={843-851},
abstract={Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-efficient solution to realize the high sampling rates required in single-chip transceivers for the emerging communication schemes: ultra-wideband, fast serial links, cognitive-radio and software-defined radio. However, the combined effects of multiple distortion sources due to channel mismatches (bandwidth, offset, gain and timing) severely affect system performance and power consumption of a TI ADC and need to be accounted for since the earlier design phases. In this paper, system-level design of TI ADCs is addressed through a platform-based methodology, enabling effective investigation of different speed/resolution scenarios as well as the impact of parallelism on accuracy, yield, sampling-rate, area and power consumption. Design space exploration of a TI successive approximation ADC is performed top-down via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing feasible implementations of the main building blocks in a 90-nm 1-V CMOS process. As a result, two implementations of the TI ADC are proposed that are capable to provide an outstanding figure-of-merit below 0.15 pJ/conversion-step.},
keywords={},
doi={10.1587/transele.E92.C.843},
ISSN={1745-1353},
month={June},}
부
TY - JOUR
TI - Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters
T2 - IEICE TRANSACTIONS on Electronics
SP - 843
EP - 851
AU - Sergio SAPONARA
AU - Pierluigi NUZZO
AU - Claudio NANI
AU - Geert VAN DER PLAS
AU - Luca FANUCCI
PY - 2009
DO - 10.1587/transele.E92.C.843
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2009
AB - Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-efficient solution to realize the high sampling rates required in single-chip transceivers for the emerging communication schemes: ultra-wideband, fast serial links, cognitive-radio and software-defined radio. However, the combined effects of multiple distortion sources due to channel mismatches (bandwidth, offset, gain and timing) severely affect system performance and power consumption of a TI ADC and need to be accounted for since the earlier design phases. In this paper, system-level design of TI ADCs is addressed through a platform-based methodology, enabling effective investigation of different speed/resolution scenarios as well as the impact of parallelism on accuracy, yield, sampling-rate, area and power consumption. Design space exploration of a TI successive approximation ADC is performed top-down via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing feasible implementations of the main building blocks in a 90-nm 1-V CMOS process. As a result, two implementations of the TI ADC are proposed that are capable to provide an outstanding figure-of-merit below 0.15 pJ/conversion-step.
ER -