The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
NBTI(네거티브 바이어스 온도 불안정성)는 고급 CMOS 기술에서 중요한 신뢰성 현상이 되었습니다. 본 논문에서는 서로 다른 온도에서 작업을 실행하고 활성 모드와 대기 모드 사이를 전환하는 두 가지 회로 작동 사례에 사용할 수 있는 분석적인 온도 인식 동적 NBTI 모델을 제안합니다. PMOS Vth 우리의 NBTI 모델을 기반으로 열화 모델과 디지털 회로의 시간적 성능 열화 추정 방법을 개발하였다. 시뮬레이션 결과는 다음을 보여줍니다. 1) 저온 작업 실행은 Δ를 감소시킬 수 있습니다.Vth NBTI로 인해 24.5%; 2) 대기 모드로 전환하면 Δ가 감소할 수 있습니다.Vth 52.3%; 3) ISCAS85 벤치마크 회로의 경우 회로가 저온 작업을 실행하거나 대기 모드로 전환하면 지연 저하가 크게 줄어들 수 있습니다. 4) 우리는 또한 다양한 작업의 실행 시간 비율과 활성 시간과 대기 시간의 비율이 모두 NBTI 효과에 상당한 영향을 미치는 것을 관찰했습니다.
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부
Hong LUO, Yu WANG, Rong LUO, Huazhong YANG, Yuan XIE, "Temperature-Aware NBTI Modeling Techniques in Digital Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 6, pp. 875-886, June 2009, doi: 10.1587/transele.E92.C.875.
Abstract: Negative bias temperature instability (NBTI) has become a critical reliability phenomena in advanced CMOS technology. In this paper, we propose an analytical temperature-aware dynamic NBTI model, which can be used in two circuit operation cases: executing tasks with different temperatures, and switching between active and standby mode. A PMOS Vth degradation model and a digital circuits' temporal performance degradation estimation method are developed based on our NBTI model. The simulation results show that: 1) the execution of a low temperature task can decrease ΔVth due to NBTI by 24.5%; 2) switching to standby mode can decrease ΔVth by 52.3%; 3) for ISCAS85 benchmark circuits, the delay degradation can decrease significantly if the circuit execute low temperature task or switch to standby mode; 4) we have also observed the execution time's ratio of different tasks and the ratio of active to standby time both have a considerable impact on NBTI effect.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.875/_p
부
@ARTICLE{e92-c_6_875,
author={Hong LUO, Yu WANG, Rong LUO, Huazhong YANG, Yuan XIE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Temperature-Aware NBTI Modeling Techniques in Digital Circuits},
year={2009},
volume={E92-C},
number={6},
pages={875-886},
abstract={Negative bias temperature instability (NBTI) has become a critical reliability phenomena in advanced CMOS technology. In this paper, we propose an analytical temperature-aware dynamic NBTI model, which can be used in two circuit operation cases: executing tasks with different temperatures, and switching between active and standby mode. A PMOS Vth degradation model and a digital circuits' temporal performance degradation estimation method are developed based on our NBTI model. The simulation results show that: 1) the execution of a low temperature task can decrease ΔVth due to NBTI by 24.5%; 2) switching to standby mode can decrease ΔVth by 52.3%; 3) for ISCAS85 benchmark circuits, the delay degradation can decrease significantly if the circuit execute low temperature task or switch to standby mode; 4) we have also observed the execution time's ratio of different tasks and the ratio of active to standby time both have a considerable impact on NBTI effect.},
keywords={},
doi={10.1587/transele.E92.C.875},
ISSN={1745-1353},
month={June},}
부
TY - JOUR
TI - Temperature-Aware NBTI Modeling Techniques in Digital Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 875
EP - 886
AU - Hong LUO
AU - Yu WANG
AU - Rong LUO
AU - Huazhong YANG
AU - Yuan XIE
PY - 2009
DO - 10.1587/transele.E92.C.875
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2009
AB - Negative bias temperature instability (NBTI) has become a critical reliability phenomena in advanced CMOS technology. In this paper, we propose an analytical temperature-aware dynamic NBTI model, which can be used in two circuit operation cases: executing tasks with different temperatures, and switching between active and standby mode. A PMOS Vth degradation model and a digital circuits' temporal performance degradation estimation method are developed based on our NBTI model. The simulation results show that: 1) the execution of a low temperature task can decrease ΔVth due to NBTI by 24.5%; 2) switching to standby mode can decrease ΔVth by 52.3%; 3) for ISCAS85 benchmark circuits, the delay degradation can decrease significantly if the circuit execute low temperature task or switch to standby mode; 4) we have also observed the execution time's ratio of different tasks and the ratio of active to standby time both have a considerable impact on NBTI effect.
ER -