The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 아날로그 회로에 탁월한 성능 향상을 제공하는 새로운 복합 트랜지스터 회로 설계 기법을 제시합니다. 캐스코드 보상 증폭기에 복합 트랜지스터를 추가함으로써 단일 102V 공급 장치에서 37.6nF의 높은 용량성 부하를 구동하면서 2dB DC 이득과 1.8MHz 단일 이득 대역폭을 달성했습니다. 성능 지수에 대한 전력 대역폭과 전력 속도 효율을 비교하면 보고된 최신 작품에 비해 상당히 높은 값을 제공합니다. 3.3V 출력 전압을 생성하기 위해 1.8V 전원으로 구동되는 선형 레귤레이터에 복합 트랜지스터를 사용함으로써 다양한 부하 전류 과도 상태에서 빠른 복구 응답을 보여 주었으며 1mA 또는 0.1mA에 대해 50μS의 100% 정착 시간을 갖습니다. mA 단계, 1Ω ESR 저항을 사용하여 0.36μF의 용량성 부하에서 최대 735mA 단계에 대해 10μS의 1% 정착 시간을 제공합니다. 시뮬레이션된 부하 조절은 0.035%이고 라인 조절은 0.488%입니다. 결과를 다른 최첨단 LDO 보고 결과와 비교하면 속도, 전류 구동 기능 및 환경 매개변수 변화에 대한 안정성 측면에서 제안된 복합 트랜지스터 기반 설계의 대폭 향상된 성능도 검증됩니다. 제안된 모든 설계는 얇은/두꺼운 산화물 옵션과 BSIM1.8 모델 매개변수를 갖춘 CSM(Chartered Semiconductor) 3.3V/0.18V 3μm CMOS 삼중 웰 공정 기술을 사용하여 시뮬레이션되었습니다.
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부
Yang TIAN, Pak Kwong CHAN, "Design of High-Performance Analog Circuits Using Wideband gm-Enhanced MOS Composite Transistors" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 7, pp. 1199-1208, July 2010, doi: 10.1587/transele.E93.C.1199.
Abstract: In this paper, we present a new composite transistor circuit design technique that provides superior performance enhancement to analog circuits. By adding a composite transistor to the cascode-compensated amplifier, it has achieved a 102 dB DC gain, and a 37.6 MHz unity gain bandwidth while driving a 2 nF heavy capacitive load at a single 1.8 V supply. In the comparison of power-bandwidth and power-speed efficiencies on figures of merit, it offers significantly high values with respect to the reported state-of-the-art works. By employing the composite transistor in a linear regulator powered by a 3.3 V supply to generate a 1.8 V output voltage, it has shown fast recovery response at various load current transients, having a 1% settling time of 0.1 µS for a 50 mA or 100 mA step, while a 1% settling time of 0.36 µS for a maximum 735 mA step under a capacitive load of 10 µF with a 1 Ω ESR resistor. The simulated load regulation is 0.035% and line regulation is 0.488%. Comparing its results with other state-of-art LDO reported results, it also validates the significant enhanced performance of the proposed composite-transistor-based design in terms of speed, current driving capability and stability against changes in environmental parameters. All the proposed designs are simulated using chartered semiconductor (CSM) 1.8 V/3.3 V 0.18 µm CMOS triple-well process technology with thin/thick oxide options and BSIM3 model parameters.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.1199/_p
부
@ARTICLE{e93-c_7_1199,
author={Yang TIAN, Pak Kwong CHAN, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of High-Performance Analog Circuits Using Wideband gm-Enhanced MOS Composite Transistors},
year={2010},
volume={E93-C},
number={7},
pages={1199-1208},
abstract={In this paper, we present a new composite transistor circuit design technique that provides superior performance enhancement to analog circuits. By adding a composite transistor to the cascode-compensated amplifier, it has achieved a 102 dB DC gain, and a 37.6 MHz unity gain bandwidth while driving a 2 nF heavy capacitive load at a single 1.8 V supply. In the comparison of power-bandwidth and power-speed efficiencies on figures of merit, it offers significantly high values with respect to the reported state-of-the-art works. By employing the composite transistor in a linear regulator powered by a 3.3 V supply to generate a 1.8 V output voltage, it has shown fast recovery response at various load current transients, having a 1% settling time of 0.1 µS for a 50 mA or 100 mA step, while a 1% settling time of 0.36 µS for a maximum 735 mA step under a capacitive load of 10 µF with a 1 Ω ESR resistor. The simulated load regulation is 0.035% and line regulation is 0.488%. Comparing its results with other state-of-art LDO reported results, it also validates the significant enhanced performance of the proposed composite-transistor-based design in terms of speed, current driving capability and stability against changes in environmental parameters. All the proposed designs are simulated using chartered semiconductor (CSM) 1.8 V/3.3 V 0.18 µm CMOS triple-well process technology with thin/thick oxide options and BSIM3 model parameters.},
keywords={},
doi={10.1587/transele.E93.C.1199},
ISSN={1745-1353},
month={July},}
부
TY - JOUR
TI - Design of High-Performance Analog Circuits Using Wideband gm-Enhanced MOS Composite Transistors
T2 - IEICE TRANSACTIONS on Electronics
SP - 1199
EP - 1208
AU - Yang TIAN
AU - Pak Kwong CHAN
PY - 2010
DO - 10.1587/transele.E93.C.1199
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2010
AB - In this paper, we present a new composite transistor circuit design technique that provides superior performance enhancement to analog circuits. By adding a composite transistor to the cascode-compensated amplifier, it has achieved a 102 dB DC gain, and a 37.6 MHz unity gain bandwidth while driving a 2 nF heavy capacitive load at a single 1.8 V supply. In the comparison of power-bandwidth and power-speed efficiencies on figures of merit, it offers significantly high values with respect to the reported state-of-the-art works. By employing the composite transistor in a linear regulator powered by a 3.3 V supply to generate a 1.8 V output voltage, it has shown fast recovery response at various load current transients, having a 1% settling time of 0.1 µS for a 50 mA or 100 mA step, while a 1% settling time of 0.36 µS for a maximum 735 mA step under a capacitive load of 10 µF with a 1 Ω ESR resistor. The simulated load regulation is 0.035% and line regulation is 0.488%. Comparing its results with other state-of-art LDO reported results, it also validates the significant enhanced performance of the proposed composite-transistor-based design in terms of speed, current driving capability and stability against changes in environmental parameters. All the proposed designs are simulated using chartered semiconductor (CSM) 1.8 V/3.3 V 0.18 µm CMOS triple-well process technology with thin/thick oxide options and BSIM3 model parameters.
ER -