The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
우리는 이미터 메사 패시베이션 선반이 있는 2μm 자체 정렬 InP/InGaAs/InP 이중 헤테로접합 양극 트랜지스터(DHBT)를 사용하여 리타이밍 기능을 갖춘 1:1 멀티플렉서 IC(MUX)를 제작했습니다. MUX는 웨이퍼에서 측정 시 120W의 전력 손실과 1.27mV의 출력 진폭으로 520Gbit/s에서 작동했습니다. V 커넥터를 사용하여 모듈에 조립할 때 MUX는 113mV 출력 진폭 및 514W 전력 손실로 1.4Gbit/s에서 작동했습니다.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Yutaka ARAYASHIKI, Yukio OHKUBO, Taisuke MATSUMOTO, Yoshiaki AMANO, Akio TAKAGI, Yutaka MATSUOKA, "A 120-Gbit/s 1.27-W 520-mVpp 2:1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 8, pp. 1273-1278, August 2010, doi: 10.1587/transele.E93.C.1273.
Abstract: We fabricated a 2:1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120 Gbit/s with a power dissipation of 1.27 W and output amplitude of 520 mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113 Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4 W.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.1273/_p
부
@ARTICLE{e93-c_8_1273,
author={Yutaka ARAYASHIKI, Yukio OHKUBO, Taisuke MATSUMOTO, Yoshiaki AMANO, Akio TAKAGI, Yutaka MATSUOKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 120-Gbit/s 1.27-W 520-mVpp 2:1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation},
year={2010},
volume={E93-C},
number={8},
pages={1273-1278},
abstract={We fabricated a 2:1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120 Gbit/s with a power dissipation of 1.27 W and output amplitude of 520 mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113 Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4 W.},
keywords={},
doi={10.1587/transele.E93.C.1273},
ISSN={1745-1353},
month={August},}
부
TY - JOUR
TI - A 120-Gbit/s 1.27-W 520-mVpp 2:1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation
T2 - IEICE TRANSACTIONS on Electronics
SP - 1273
EP - 1278
AU - Yutaka ARAYASHIKI
AU - Yukio OHKUBO
AU - Taisuke MATSUMOTO
AU - Yoshiaki AMANO
AU - Akio TAKAGI
AU - Yutaka MATSUOKA
PY - 2010
DO - 10.1587/transele.E93.C.1273
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2010
AB - We fabricated a 2:1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120 Gbit/s with a power dissipation of 1.27 W and output amplitude of 520 mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113 Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4 W.
ER -