The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 문서에서는 LDO(저드롭아웃 조정기)의 설계 방법론을 설명합니다. 이는 본 문서에서도 설명하는 CDMA 핸드셋용 전원 관리 하위 시스템 IC를 개발하는 데 사용되었습니다. 이 IC에는 11개의 LDO, 밴드갭 레퍼런스, 배터리 충전기, 제어 로직 및 기타 주변 회로가 포함되어 있습니다. CDMA 애플리케이션의 경우 LDO에는 대기 모드에서 µA 정도의 매우 작은 접지 전류가 필요합니다. 이러한 요구 사항을 충족하고 프로세스 변화에 따라 안정적인 작동을 달성하기 위한 LDO 아키텍처가 개발되었습니다. 온칩 로직은 모든 LDO와 배터리 충전기를 효율적으로 제어하여 전력 소모를 최대한 줄입니다. 이 혼합 신호 하위 시스템은 사내 0.6μm BCDMOS 프로세스에서 구현되었습니다. 안정적인 작동으로 3μA까지 매우 낮은 LDO 접지 전류가 달성되었습니다.
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부
Tsutomu WAKIMOTO, "LDO Design Methodology and an Intelligent Power Management Sub-System IC for CDMA Handsets" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 10, pp. 1518-1524, October 2010, doi: 10.1587/transele.E93.C.1518.
Abstract: This paper describes the design methodology of a low dropout regulator (LDO). It was used to develop a power management sub-system IC for CDMA handsets which is also described in this paper. This IC contains 11 LDOs, bandgap reference, battery charger, control logic and some other peripheral circuits. For CDMA applications, very small ground current in the order of µA in standby mode is required for LDOs. An LDO architecture to meet this requirement and achieve stable operation over the process variation was developed. The on-chip logic efficiently controls all LDOs and battery charger to reduce the power dissipation as much as possible. This mixed signal subsystem has been implemented in the in-house 0.6-µm BCDMOS process. The very low LDO ground current down to 3 µA has been achieved with stable operation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.1518/_p
부
@ARTICLE{e93-c_10_1518,
author={Tsutomu WAKIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={LDO Design Methodology and an Intelligent Power Management Sub-System IC for CDMA Handsets},
year={2010},
volume={E93-C},
number={10},
pages={1518-1524},
abstract={This paper describes the design methodology of a low dropout regulator (LDO). It was used to develop a power management sub-system IC for CDMA handsets which is also described in this paper. This IC contains 11 LDOs, bandgap reference, battery charger, control logic and some other peripheral circuits. For CDMA applications, very small ground current in the order of µA in standby mode is required for LDOs. An LDO architecture to meet this requirement and achieve stable operation over the process variation was developed. The on-chip logic efficiently controls all LDOs and battery charger to reduce the power dissipation as much as possible. This mixed signal subsystem has been implemented in the in-house 0.6-µm BCDMOS process. The very low LDO ground current down to 3 µA has been achieved with stable operation.},
keywords={},
doi={10.1587/transele.E93.C.1518},
ISSN={1745-1353},
month={October},}
부
TY - JOUR
TI - LDO Design Methodology and an Intelligent Power Management Sub-System IC for CDMA Handsets
T2 - IEICE TRANSACTIONS on Electronics
SP - 1518
EP - 1524
AU - Tsutomu WAKIMOTO
PY - 2010
DO - 10.1587/transele.E93.C.1518
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2010
AB - This paper describes the design methodology of a low dropout regulator (LDO). It was used to develop a power management sub-system IC for CDMA handsets which is also described in this paper. This IC contains 11 LDOs, bandgap reference, battery charger, control logic and some other peripheral circuits. For CDMA applications, very small ground current in the order of µA in standby mode is required for LDOs. An LDO architecture to meet this requirement and achieve stable operation over the process variation was developed. The on-chip logic efficiently controls all LDOs and battery charger to reduce the power dissipation as much as possible. This mixed signal subsystem has been implemented in the in-house 0.6-µm BCDMOS process. The very low LDO ground current down to 3 µA has been achieved with stable operation.
ER -