The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
적층 가능한 다층 3TXR 메모리 셀 구조를 사용하는 새로운 1D RRAM 개념이 제안되었습니다. 액세스 트랜지스터는 표준 CMOS 프로세스에 대한 친화력이 뛰어난 실리콘으로 제작됩니다. 8TXR을 적층한 1겹의 금속을 사용(X=64) 일례로 기존 단층 260T1R 구조에 비해 밀도가 1% 이상 높다. 또한, 몰래 전류로 인한 잘못된 쓰기 및 읽기를 효과적으로 방지하고 전력 소비를 줄일 수 있는 해당 동작 알고리즘이 제시됩니다.
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부
Ji ZHANG, Yiqing DING, Xiaoyong XUE, Gang JIN, Yuxin WU, Yufeng XIE, Yinyin LIN, "A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 12, pp. 1692-1699, December 2010, doi: 10.1587/transele.E93.C.1692.
Abstract: A novel 3D RRAM concept using a stackable multi-layer 1TXR memory cell structure is proposed. The access transistor is fabricated in silicon, which has excellent affinity to the standard CMOS process. Using an 8-layer metal of stacked 1TXR (X=64) as an example, the density is over 260% higher than that of the conventional single layer 1T1R structure. Further, a corresponding operation algorithm is put forward, which can inhibit effectively mis-write and mis-read caused by sneaking current and reduce power consumption.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.1692/_p
부
@ARTICLE{e93-c_12_1692,
author={Ji ZHANG, Yiqing DING, Xiaoyong XUE, Gang JIN, Yuxin WU, Yufeng XIE, Yinyin LIN, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell},
year={2010},
volume={E93-C},
number={12},
pages={1692-1699},
abstract={A novel 3D RRAM concept using a stackable multi-layer 1TXR memory cell structure is proposed. The access transistor is fabricated in silicon, which has excellent affinity to the standard CMOS process. Using an 8-layer metal of stacked 1TXR (X=64) as an example, the density is over 260% higher than that of the conventional single layer 1T1R structure. Further, a corresponding operation algorithm is put forward, which can inhibit effectively mis-write and mis-read caused by sneaking current and reduce power consumption.},
keywords={},
doi={10.1587/transele.E93.C.1692},
ISSN={1745-1353},
month={December},}
부
TY - JOUR
TI - A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell
T2 - IEICE TRANSACTIONS on Electronics
SP - 1692
EP - 1699
AU - Ji ZHANG
AU - Yiqing DING
AU - Xiaoyong XUE
AU - Gang JIN
AU - Yuxin WU
AU - Yufeng XIE
AU - Yinyin LIN
PY - 2010
DO - 10.1587/transele.E93.C.1692
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2010
AB - A novel 3D RRAM concept using a stackable multi-layer 1TXR memory cell structure is proposed. The access transistor is fabricated in silicon, which has excellent affinity to the standard CMOS process. Using an 8-layer metal of stacked 1TXR (X=64) as an example, the density is over 260% higher than that of the conventional single layer 1T1R structure. Further, a corresponding operation algorithm is put forward, which can inhibit effectively mis-write and mis-read caused by sneaking current and reduce power consumption.
ER -