The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
IEEE802.15.3c 밀리미터파 무선 개인 영역 네트워크(WPAN) 애플리케이션을 위한 혼합 모드 고속 BPSK(Binary Phase-Shift Keying) 복조기는 0.18μm CMOS 프로세스로 구현됩니다. 제안된 복조기 방식은 ADC(아날로그-디지털 변환기)가 필요하지 않으므로 고속 데이터 복조에 있어 기존 방식에 비해 장점을 가질 수 있습니다. 복조기 코어는 53.8V 전원 공급 장치에서 2.5mW를 소비하고 칩 면적은 380mW입니다.
이진 위상 편이 키잉, BPSK, 모뎀, 복조기, IEEE802.15.3c, 무선팬
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
부
Kwang-Chun CHOI, Minsu KO, Duho KIM, Woo-Young CHOI, "Demonstration of 60-GHz Link Using a 1.6-Gb/s Mixed-Mode BPSK Demodulator" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 12, pp. 1704-1707, December 2010, doi: 10.1587/transele.E93.C.1704.
Abstract: A mixed-mode high-speed binary phase-shift keying (BPSK) demodulator for IEEE802.15.3c mm-wave wireless personal area network (WPAN) application is realized with 0.18-µm CMOS process. The proposed demodulator scheme does not require any analog-to-digital converters (ADC) and, consequently, can have advantages over the conventional schemes for high-data-rate demodulation. The demodulator core consumes 53.8 mW from 2.5-V power supply while the chip area is 380
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.1704/_p
부
@ARTICLE{e93-c_12_1704,
author={Kwang-Chun CHOI, Minsu KO, Duho KIM, Woo-Young CHOI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Demonstration of 60-GHz Link Using a 1.6-Gb/s Mixed-Mode BPSK Demodulator},
year={2010},
volume={E93-C},
number={12},
pages={1704-1707},
abstract={A mixed-mode high-speed binary phase-shift keying (BPSK) demodulator for IEEE802.15.3c mm-wave wireless personal area network (WPAN) application is realized with 0.18-µm CMOS process. The proposed demodulator scheme does not require any analog-to-digital converters (ADC) and, consequently, can have advantages over the conventional schemes for high-data-rate demodulation. The demodulator core consumes 53.8 mW from 2.5-V power supply while the chip area is 380
keywords={},
doi={10.1587/transele.E93.C.1704},
ISSN={1745-1353},
month={December},}
부
TY - JOUR
TI - Demonstration of 60-GHz Link Using a 1.6-Gb/s Mixed-Mode BPSK Demodulator
T2 - IEICE TRANSACTIONS on Electronics
SP - 1704
EP - 1707
AU - Kwang-Chun CHOI
AU - Minsu KO
AU - Duho KIM
AU - Woo-Young CHOI
PY - 2010
DO - 10.1587/transele.E93.C.1704
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2010
AB - A mixed-mode high-speed binary phase-shift keying (BPSK) demodulator for IEEE802.15.3c mm-wave wireless personal area network (WPAN) application is realized with 0.18-µm CMOS process. The proposed demodulator scheme does not require any analog-to-digital converters (ADC) and, consequently, can have advantages over the conventional schemes for high-data-rate demodulation. The demodulator core consumes 53.8 mW from 2.5-V power supply while the chip area is 380
ER -