The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
7비트 1.0Gsps 캐스케이드 폴딩 ADC가 제공됩니다. 이 ADC는 3도 폴더가 있는 계단식 폴딩 아키텍처를 사용합니다. 새로운 리셋 기술과 레이아웃 셔플링을 통해 ADC는 낮은 전력 소비로 고속으로 작동할 수 있습니다. 90nm CMOS 프로세스 기술로 구현된 ADC는 230V 및 1.2V 공급 장치에서 2.5mW를 소비하고 SNR은 38dB입니다.
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Koichi ONO, Takeshi OHKAWA, Masahiro SEGAMI, Masao HOTTA, "A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 3, pp. 288-294, March 2010, doi: 10.1587/transele.E93.C.288.
Abstract: A 7 bit 1.0 Gsps Cascaded Folding ADC is presented. This ADC employs cascaded folding architecture with 3-degree folders. A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption. Implemented in a 90 nm CMOS process technology the ADC consumes 230 mW with 1.2 V and 2.5 V supplies and has a SNR of 38 dB.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.288/_p
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@ARTICLE{e93-c_3_288,
author={Koichi ONO, Takeshi OHKAWA, Masahiro SEGAMI, Masao HOTTA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique},
year={2010},
volume={E93-C},
number={3},
pages={288-294},
abstract={A 7 bit 1.0 Gsps Cascaded Folding ADC is presented. This ADC employs cascaded folding architecture with 3-degree folders. A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption. Implemented in a 90 nm CMOS process technology the ADC consumes 230 mW with 1.2 V and 2.5 V supplies and has a SNR of 38 dB.},
keywords={},
doi={10.1587/transele.E93.C.288},
ISSN={1745-1353},
month={March},}
부
TY - JOUR
TI - A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique
T2 - IEICE TRANSACTIONS on Electronics
SP - 288
EP - 294
AU - Koichi ONO
AU - Takeshi OHKAWA
AU - Masahiro SEGAMI
AU - Masao HOTTA
PY - 2010
DO - 10.1587/transele.E93.C.288
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2010
AB - A 7 bit 1.0 Gsps Cascaded Folding ADC is presented. This ADC employs cascaded folding architecture with 3-degree folders. A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption. Implemented in a 90 nm CMOS process technology the ADC consumes 230 mW with 1.2 V and 2.5 V supplies and has a SNR of 38 dB.
ER -