The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
공정 스케일링에 따라 반도체 소자는 임계 전하량이 감소함에 따라 소프트 오류에 더욱 민감해지고 있습니다. 본 논문에서는 SEU(Single Event Upset)와 SET(Single Event Transient)에 견딜 수 있는 면적/지연 효율적인 이중 모듈형 플립플롭을 제안한다. 이는 "BISER"(내장 소프트 오류 복원력)를 기반으로 합니다. 원래의 BISER FF는 작은 면적을 달성하지만 C 요소의 SET 펄스에 취약합니다. 제안된 듀얼 모듈러 FF는 C 요소와 마스터 래치와 슬레이브 래치 사이의 약한 키퍼를 두 배로 늘려 기존 지연 TMR FF보다 작은 영역 지연 제품을 지불하여 SET 내성을 상당히 향상시킵니다.
NMR, 내장된 소프트 오류, 당신의, SET를
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Jun FURUTA, Kazutoshi KOBAYASHI, Hidetoshi ONODERA, "An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 3, pp. 340-346, March 2010, doi: 10.1587/transele.E93.C.340.
Abstract: According to the process scaling, semiconductor devices are becoming more sensitive to soft errors since amount of critical charges are decreasing. In this paper, we propose an area/delay efficient dual modular flip-flop, which is tolerant to SEU (Single Event Upset) and SET (Single Event Transient). It is based on a "BISER" (Built-in Soft Error Resilience). The original BISER FF achieves small area but it is vulnerable to an SET pulse on C-elements. The proposed dual modular FF doubles C-elements and weak keepers between master and slave latches, which enhances SET immunity considerably with paying small area-delay product than the conventional delayed TMR FFs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.340/_p
부
@ARTICLE{e93-c_3_340,
author={Jun FURUTA, Kazutoshi KOBAYASHI, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity},
year={2010},
volume={E93-C},
number={3},
pages={340-346},
abstract={According to the process scaling, semiconductor devices are becoming more sensitive to soft errors since amount of critical charges are decreasing. In this paper, we propose an area/delay efficient dual modular flip-flop, which is tolerant to SEU (Single Event Upset) and SET (Single Event Transient). It is based on a "BISER" (Built-in Soft Error Resilience). The original BISER FF achieves small area but it is vulnerable to an SET pulse on C-elements. The proposed dual modular FF doubles C-elements and weak keepers between master and slave latches, which enhances SET immunity considerably with paying small area-delay product than the conventional delayed TMR FFs.},
keywords={},
doi={10.1587/transele.E93.C.340},
ISSN={1745-1353},
month={March},}
부
TY - JOUR
TI - An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity
T2 - IEICE TRANSACTIONS on Electronics
SP - 340
EP - 346
AU - Jun FURUTA
AU - Kazutoshi KOBAYASHI
AU - Hidetoshi ONODERA
PY - 2010
DO - 10.1587/transele.E93.C.340
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2010
AB - According to the process scaling, semiconductor devices are becoming more sensitive to soft errors since amount of critical charges are decreasing. In this paper, we propose an area/delay efficient dual modular flip-flop, which is tolerant to SEU (Single Event Upset) and SET (Single Event Transient). It is based on a "BISER" (Built-in Soft Error Resilience). The original BISER FF achieves small area but it is vulnerable to an SET pulse on C-elements. The proposed dual modular FF doubles C-elements and weak keepers between master and slave latches, which enhances SET immunity considerably with paying small area-delay product than the conventional delayed TMR FFs.
ER -