The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
10nm 게이트 Multi-Nano-Pillar형(M-) 수직 MOSFET의 뛰어난 성능이 처음으로 수치로 나타났습니다. M-Vertical MOSFET은 기존의 Single Pillar형(S-)Vertical MOSFET에 비해 구동 전류가 2배 이상 증가하고 거의 이상적인 S-factor와 억제된 컷오프를 달성했음이 분명합니다. 단채널 효과와 DIBL 효과를 모두 억제하여 누설 전류를 1/60 미만으로 줄였습니다. 또한 M-Vertical MOSFET의 이러한 개선 메커니즘이 명확해졌습니다. 위의 모든 것에서 M-Vertical MOSFET은 10nm 미만 세대의 미래 고속 및 저전력 LSI를 위한 핵심 장치 후보라는 것이 나타났습니다.
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Tetsuo ENDOH, Koji SAKUI, Yukio YASUDA, "Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 5, pp. 557-562, May 2010, doi: 10.1587/transele.E93.C.557.
Abstract: The excellent performance of the 10 nm gate Multi-Nano-Pillar type (M-) Vertical MOSFET has been numerically shown for the first time. It is made clear that the M-Vertical MOSFET, in comparison with the conventional Single Pillar type (S-) Vertical MOSFET, has achieved an increased driving current by more than 2 times, a nearly ideal S-factor, and a suppressed cutoff-leakage current by less than 1/60 by suppressing both the short channel effect and the DIBL effect. Moreover, mechanisms of these improvements of the M-Vertical MOSFET are made clear. From all of the above, it is shown that the M-Vertical MOSFET is a key device candidate for future high speed and low power LSI's in the sub-10 nm generation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.557/_p
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@ARTICLE{e93-c_5_557,
author={Tetsuo ENDOH, Koji SAKUI, Yukio YASUDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET},
year={2010},
volume={E93-C},
number={5},
pages={557-562},
abstract={The excellent performance of the 10 nm gate Multi-Nano-Pillar type (M-) Vertical MOSFET has been numerically shown for the first time. It is made clear that the M-Vertical MOSFET, in comparison with the conventional Single Pillar type (S-) Vertical MOSFET, has achieved an increased driving current by more than 2 times, a nearly ideal S-factor, and a suppressed cutoff-leakage current by less than 1/60 by suppressing both the short channel effect and the DIBL effect. Moreover, mechanisms of these improvements of the M-Vertical MOSFET are made clear. From all of the above, it is shown that the M-Vertical MOSFET is a key device candidate for future high speed and low power LSI's in the sub-10 nm generation.},
keywords={},
doi={10.1587/transele.E93.C.557},
ISSN={1745-1353},
month={May},}
부
TY - JOUR
TI - Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET
T2 - IEICE TRANSACTIONS on Electronics
SP - 557
EP - 562
AU - Tetsuo ENDOH
AU - Koji SAKUI
AU - Yukio YASUDA
PY - 2010
DO - 10.1587/transele.E93.C.557
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2010
AB - The excellent performance of the 10 nm gate Multi-Nano-Pillar type (M-) Vertical MOSFET has been numerically shown for the first time. It is made clear that the M-Vertical MOSFET, in comparison with the conventional Single Pillar type (S-) Vertical MOSFET, has achieved an increased driving current by more than 2 times, a nearly ideal S-factor, and a suppressed cutoff-leakage current by less than 1/60 by suppressing both the short channel effect and the DIBL effect. Moreover, mechanisms of these improvements of the M-Vertical MOSFET are made clear. From all of the above, it is shown that the M-Vertical MOSFET is a key device candidate for future high speed and low power LSI's in the sub-10 nm generation.
ER -