The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
저전력 TCAM(Ternary Content Addressable Memory) 아키텍처가 제안되었습니다. TCAM은 검색 및 정렬 처리를 위한 강력한 엔진이지만 전력 소비가 크고 전력선 잡음이 크다는 두 가지 심각한 문제가 있습니다. 이러한 문제를 해결하기 위해 우리는 매치라인과 검색라인에 대한 전하 재활용 방식을 개발했습니다. 새로 도입된 PMOS CAM 셀과 기존 NMOS CAM 셀을 결합하면 매치 라인 전하 재활용이 실현됩니다. NMOS와 PMOS 셀 어레이의 체커보드 배열은 검색 라인 전하 재활용을 가능하게 합니다. 이러한 기술을 사용하면 TCAM의 전력 소비를 기존 설계의 50%로 줄일 수 있으며 결과적으로 전력선 노이즈도 감소합니다. 실험적인 칩은 180nm 6-금속 공정으로 제작되었습니다. 이 칩의 전력 소비는 6.3 fJ/bit/search로 기존 방식의 절반입니다.
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Katsumi DOSAKA, Daisuke OGAWA, Takahito KUSUMOTO, Masayuki MIYAMA, Yoshio MATSUDA, "A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 5, pp. 685-695, May 2010, doi: 10.1587/transele.E93.C.685.
Abstract: Architecture of a low power Ternary Content Addressable Memory (TCAM) is proposed. The TCAM is a powerful engine for search and sort processing, but it has two serious problems, large power consumption and large power line noise. To solve these problems, we have developed a charge recycling scheme for match lines and search lines. A combination of the newly introduced PMOS CAM cell together with the conventional NMOS CAM cell realizes match line charge recycling. A checkerboard arrangement of the NMOS and the PMOS cell array enables search line charge recycling. By using these technologies, the power consumption of the TCAM can be reduced to 50% of conventional designs, and as a result, the power line noise is also reduced. An experimental chip has been fabricated in 180-nm 6-metal process. The power consumption of this chip is 6.3 fJ/bit/search, which is half of the conventional scheme.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.685/_p
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@ARTICLE{e93-c_5_685,
author={Katsumi DOSAKA, Daisuke OGAWA, Takahito KUSUMOTO, Masayuki MIYAMA, Yoshio MATSUDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications},
year={2010},
volume={E93-C},
number={5},
pages={685-695},
abstract={Architecture of a low power Ternary Content Addressable Memory (TCAM) is proposed. The TCAM is a powerful engine for search and sort processing, but it has two serious problems, large power consumption and large power line noise. To solve these problems, we have developed a charge recycling scheme for match lines and search lines. A combination of the newly introduced PMOS CAM cell together with the conventional NMOS CAM cell realizes match line charge recycling. A checkerboard arrangement of the NMOS and the PMOS cell array enables search line charge recycling. By using these technologies, the power consumption of the TCAM can be reduced to 50% of conventional designs, and as a result, the power line noise is also reduced. An experimental chip has been fabricated in 180-nm 6-metal process. The power consumption of this chip is 6.3 fJ/bit/search, which is half of the conventional scheme.},
keywords={},
doi={10.1587/transele.E93.C.685},
ISSN={1745-1353},
month={May},}
부
TY - JOUR
TI - A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 685
EP - 695
AU - Katsumi DOSAKA
AU - Daisuke OGAWA
AU - Takahito KUSUMOTO
AU - Masayuki MIYAMA
AU - Yoshio MATSUDA
PY - 2010
DO - 10.1587/transele.E93.C.685
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2010
AB - Architecture of a low power Ternary Content Addressable Memory (TCAM) is proposed. The TCAM is a powerful engine for search and sort processing, but it has two serious problems, large power consumption and large power line noise. To solve these problems, we have developed a charge recycling scheme for match lines and search lines. A combination of the newly introduced PMOS CAM cell together with the conventional NMOS CAM cell realizes match line charge recycling. A checkerboard arrangement of the NMOS and the PMOS cell array enables search line charge recycling. By using these technologies, the power consumption of the TCAM can be reduced to 50% of conventional designs, and as a result, the power line noise is also reduced. An experimental chip has been fabricated in 180-nm 6-metal process. The power consumption of this chip is 6.3 fJ/bit/search, which is half of the conventional scheme.
ER -