The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
새로운 고속 잠금, 저전력 디지털 지연 잠금 루프(DLL)가 제공됩니다. 단 0.13개의 클록 사이클 내에서 루프를 효과적으로 잠그기 위해 하위 범위 검색 알고리즘이 사용됩니다. 전력 소모를 줄이기 위해 반지연 회로를 사용합니다. 표준 50μm CMOS 프로세스의 프로토타입 DLL은 400개의 클록 사이클 잠금 시간으로 2.379MHz ~ 1MHz 범위에서 작동하며 400MHz 클록 속도에서 400V 전원으로 1.586mW를 소비합니다. 16.67MHz에서 측정된 RMS 지터와 피크 대 피크 지터는 각각 0.038ps와 XNUMXps입니다. XNUMXmm의 활성 영역을 차지합니다.2.
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부
Hsin-Shu CHEN, Jyun-Cheng LIN, "A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 6, pp. 855-860, June 2010, doi: 10.1587/transele.E93.C.855.
Abstract: A new fast-lock, low-power digital delay-locked loop (DLL) is presented. A subranging searching algorithm is employed to effectively make the loop locked within only four clock cycles. A half-delay circuit is utilized to cut down power consumption. The prototype DLL in a standard 0.13-µm CMOS process operates in the range from 50 MHz to 400 MHz with four clock cycle lock time and consumes 2.379 mW with 1-V supply at 400 MHz clock rate. The measured RMS jitter and peak-to-peak jitter at 400 MHz are 1.586 ps and 16.67 ps, respectively. It occupies an active area of 0.038 mm2.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.855/_p
부
@ARTICLE{e93-c_6_855,
author={Hsin-Shu CHEN, Jyun-Cheng LIN, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop},
year={2010},
volume={E93-C},
number={6},
pages={855-860},
abstract={A new fast-lock, low-power digital delay-locked loop (DLL) is presented. A subranging searching algorithm is employed to effectively make the loop locked within only four clock cycles. A half-delay circuit is utilized to cut down power consumption. The prototype DLL in a standard 0.13-µm CMOS process operates in the range from 50 MHz to 400 MHz with four clock cycle lock time and consumes 2.379 mW with 1-V supply at 400 MHz clock rate. The measured RMS jitter and peak-to-peak jitter at 400 MHz are 1.586 ps and 16.67 ps, respectively. It occupies an active area of 0.038 mm2.},
keywords={},
doi={10.1587/transele.E93.C.855},
ISSN={1745-1353},
month={June},}
부
TY - JOUR
TI - A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop
T2 - IEICE TRANSACTIONS on Electronics
SP - 855
EP - 860
AU - Hsin-Shu CHEN
AU - Jyun-Cheng LIN
PY - 2010
DO - 10.1587/transele.E93.C.855
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2010
AB - A new fast-lock, low-power digital delay-locked loop (DLL) is presented. A subranging searching algorithm is employed to effectively make the loop locked within only four clock cycles. A half-delay circuit is utilized to cut down power consumption. The prototype DLL in a standard 0.13-µm CMOS process operates in the range from 50 MHz to 400 MHz with four clock cycle lock time and consumes 2.379 mW with 1-V supply at 400 MHz clock rate. The measured RMS jitter and peak-to-peak jitter at 400 MHz are 1.586 ps and 16.67 ps, respectively. It occupies an active area of 0.038 mm2.
ER -