The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
저전압 작동과 더 긴 데이터 보존 시간을 위해 새로운 1트랜지스터 동적 랜덤 액세스 메모리(1T DRAM) 셀이 제안되었습니다. 제안된 1T DRAM 셀은 기존 XNUMXT DRAM 셀과 비교하여 낮은 바디 도핑 농도, 리세스형 게이트 구조, P형의 세 가지 특징을 가지고 있습니다. + 폴리시 게이트. 시뮬레이션 결과는 제안된 1T DRAM 셀이 1V 이하의 작동 전압 조건에서 < 100ns의 프로그램 시간과 > 1ms의 데이터 유지 시간을 가짐을 보여줍니다.
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부
Woojun LEE, Kwangsoo KIM, Woo Young CHOI, "Novel 1T DRAM Cell for Low-Voltage Operation and Long Data Retention Time" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 1, pp. 110-115, January 2011, doi: 10.1587/transele.E94.C.110.
Abstract: A novel one-transistor dynamic random access memory (1T DRAM) cell has been proposed for a low-voltage operation and longer data retention time. The proposed 1T DRAM cell has three features compared with a conventional 1T DRAM cell: low body doping concentration, a recessed gate structure, and a P + poly-Si gate. Simulation results show that the proposed 1T DRAM cell has < 1-ns program time and > 100-ms data retention time under the condition of sub-1-V operating voltage.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.110/_p
부
@ARTICLE{e94-c_1_110,
author={Woojun LEE, Kwangsoo KIM, Woo Young CHOI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Novel 1T DRAM Cell for Low-Voltage Operation and Long Data Retention Time},
year={2011},
volume={E94-C},
number={1},
pages={110-115},
abstract={A novel one-transistor dynamic random access memory (1T DRAM) cell has been proposed for a low-voltage operation and longer data retention time. The proposed 1T DRAM cell has three features compared with a conventional 1T DRAM cell: low body doping concentration, a recessed gate structure, and a P + poly-Si gate. Simulation results show that the proposed 1T DRAM cell has < 1-ns program time and > 100-ms data retention time under the condition of sub-1-V operating voltage.},
keywords={},
doi={10.1587/transele.E94.C.110},
ISSN={1745-1353},
month={January},}
부
TY - JOUR
TI - Novel 1T DRAM Cell for Low-Voltage Operation and Long Data Retention Time
T2 - IEICE TRANSACTIONS on Electronics
SP - 110
EP - 115
AU - Woojun LEE
AU - Kwangsoo KIM
AU - Woo Young CHOI
PY - 2011
DO - 10.1587/transele.E94.C.110
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2011
AB - A novel one-transistor dynamic random access memory (1T DRAM) cell has been proposed for a low-voltage operation and longer data retention time. The proposed 1T DRAM cell has three features compared with a conventional 1T DRAM cell: low body doping concentration, a recessed gate structure, and a P + poly-Si gate. Simulation results show that the proposed 1T DRAM cell has < 1-ns program time and > 100-ms data retention time under the condition of sub-1-V operating voltage.
ER -