The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 SFQ 논리 회로를 위한 레이아웃 중심의 왜곡된 클록 트리 합성 방법을 제안한다. 클록 트리가 없는 주어진 논리 회로의 경우, 우리의 알고리즘은 합성된 클록 트리와 주어진 클록 주기 및 클록 게이트의 대략적인 배치를 달성하는 타이밍 조정이 있는 회로를 출력합니다. 제안된 알고리즘에서는 클록된 게이트를 레벨별로 그룹화하고 각 레벨별로 클록 트리를 합성한다. 각 레벨에 대해 각 게이트의 가능한 모든 배치에 대한 클럭 타이밍을 추정한 다음 타이밍 조정을 위해 총 지연 요소 수를 최소화하는 모든 게이트의 배치를 검색합니다. 배치가 이루어지면 와이어 교차점이 없는 시계 트리를 합성합니다. 제안된 방법을 적당한 크기의 회로에 적용하여 주어진 타이밍 요구 사항을 만족하는 클록 트리가 자동으로 합성될 수 있음을 확인했습니다.
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부
Kazuyoshi TAKAGI, Yuki ITO, Shota TAKESHIMA, Masamitsu TANAKA, Naofumi TAKAGI, "Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 3, pp. 288-295, March 2011, doi: 10.1587/transele.E94.C.288.
Abstract: In this paper, we propose a method for layout-driven skewed clock tree synthesis for SFQ logic circuits. For a given logic circuit without a clock tree, our algorithm outputs a circuit with a synthesized clock tree and timing adjustments achieving the given clock period and a rough placement of the clocked gates. In the proposed algorithm, clocked gates are grouped into levels and the clock tree is synthesized for each level. For each level, we estimate the clock timing for all possible placements of each gate, and then we search a placement of all gates that minimizes the total number of delay elements for timing adjustment. Once the placement is obtained, we synthesize a clock tree without wire intersections. We applied the proposed method to a moderate size circuit and confirmed that clock trees satisfying given timing requirements can be synthesized automatically.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.288/_p
부
@ARTICLE{e94-c_3_288,
author={Kazuyoshi TAKAGI, Yuki ITO, Shota TAKESHIMA, Masamitsu TANAKA, Naofumi TAKAGI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits},
year={2011},
volume={E94-C},
number={3},
pages={288-295},
abstract={In this paper, we propose a method for layout-driven skewed clock tree synthesis for SFQ logic circuits. For a given logic circuit without a clock tree, our algorithm outputs a circuit with a synthesized clock tree and timing adjustments achieving the given clock period and a rough placement of the clocked gates. In the proposed algorithm, clocked gates are grouped into levels and the clock tree is synthesized for each level. For each level, we estimate the clock timing for all possible placements of each gate, and then we search a placement of all gates that minimizes the total number of delay elements for timing adjustment. Once the placement is obtained, we synthesize a clock tree without wire intersections. We applied the proposed method to a moderate size circuit and confirmed that clock trees satisfying given timing requirements can be synthesized automatically.},
keywords={},
doi={10.1587/transele.E94.C.288},
ISSN={1745-1353},
month={March},}
부
TY - JOUR
TI - Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 288
EP - 295
AU - Kazuyoshi TAKAGI
AU - Yuki ITO
AU - Shota TAKESHIMA
AU - Masamitsu TANAKA
AU - Naofumi TAKAGI
PY - 2011
DO - 10.1587/transele.E94.C.288
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2011
AB - In this paper, we propose a method for layout-driven skewed clock tree synthesis for SFQ logic circuits. For a given logic circuit without a clock tree, our algorithm outputs a circuit with a synthesized clock tree and timing adjustments achieving the given clock period and a rough placement of the clocked gates. In the proposed algorithm, clocked gates are grouped into levels and the clock tree is synthesized for each level. For each level, we estimate the clock timing for all possible placements of each gate, and then we search a placement of all gates that minimizes the total number of delay elements for timing adjustment. Once the placement is obtained, we synthesize a clock tree without wire intersections. We applied the proposed method to a moderate size circuit and confirmed that clock trees satisfying given timing requirements can be synthesized automatically.
ER -