The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
우리는 다음을 사용하여 고속 및 저전력 OTA(Operational Transconductance Amplifier)에 대한 설계 최적화 흐름을 제안합니다. gm/ID 스케일링된 CMOS의 조회 테이블 설계 방법론. 이 방법론은 gm/ID 1차 설계 파라미터로 강, 중, 약 반전 영역 등 모든 동작 영역을 고려하여 최저 전력 설계가 가능합니다. SPICE 기반 조회 테이블 접근 방식을 사용하여 지정된 작업 영역을 최적화합니다. gm/ID 단채널 트랜지스터에 대해 충분한 정확도를 제공합니다. 최적화된 설계 흐름의 특징은 1) 사양에 대한 최악의 설계 시나리오 제안과 gm/ID 최악의 SPICE 시뮬레이션에서 조회 테이블 생성, 2) 회로 매개변수의 조정을 제거하기 위해 분석 및 시뮬레이션 기반 접근 방식을 결합하여 수행한 최적화 절차, 3) 추가 사용 gm/ID 2차 효과를 고려한 서브플롯. 복잡한 토폴로지를 갖는 회로에 대해 제안된 설계 방법론의 효율성을 탐색하기 위해 스위치드 커패시터 회로에 대한 게인 부스트 접이식 캐스코드 OTA가 대상 토폴로지로 채택되었습니다. 이득 부스트 폴디드 캐스코드 OTA의 DC 이득, 주파수 응답 및 출력 잡음에 대한 분석적 표현이 제시되고, 세부적인 최적화가 제시됩니다. gm/IDs 및 회로 매개변수가 설명되어 있습니다. 10μm CMOS 기술로 구현된 125비트 0.18MS/s 파이프라인 A/D 변환기의 잔여 증폭기에 대한 적용에 대한 최적화 흐름이 검증되었습니다. 최적화된 회로는 회로 매개변수를 추가로 조정하지 않고도 모든 코너 시뮬레이션에 필요한 사양을 충족합니다. 마지막으로 이 설계 방법론을 기술 마이그레이션 도구로 적용할 수 있는 가능성을 탐색하고, 차이점을 비교하여 실패 분석을 설명합니다. gm/ID 형질.
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Takayuki KONISHI, Kenji INAZU, Jun Gyu LEE, Masanori NATSUI, Shoichi MASUI, Boris MURMANN, "Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 3, pp. 334-345, March 2011, doi: 10.1587/transele.E94.C.334.
Abstract: We propose a design optimization flow for a high-speed and low-power operational transconductance amplifier (OTA) using a gm/ID lookup table design methodology in scaled CMOS. This methodology advantages from using gm/ID as a primary design parameter to consider all operation regions including strong, moderate, and weak inversion regions, and enables the lowest power design. SPICE-based lookup table approach is employed to optimize the operation region specified by the gm/ID with sufficient accuracy for short-channel transistors. The optimized design flow features 1) a proposal of the worst-case design scenario for specification and gm/ID lookup table generations from worst-case SPICE simulations, 2) an optimization procedure accomplished by the combination of analytical and simulation-based approaches in order to eliminate tweaking of circuit parameters, and 3) an additional use of gm/ID subplots to take second-order effects into account. A gain-boosted folded-cascode OTA for a switched capacitor circuit is adopted as a target topology to explore the effectiveness of the proposed design methodology for a circuit with complex topology. Analytical expressions of the gain-boosted folded-cascode OTA in terms of DC gain, frequency response and output noise are presented, and detailed optimization of gm/IDs as well as circuit parameters are illustrated. The optimization flow is verified for the application to a residue amplifier in a 10-bit 125 MS/s pipeline A/D converter implemented in a 0.18 µm CMOS technology. The optimized circuit satisfies the required specification for all corner simulations without additional tweaking of circuit parameters. We finally explore the possibility of applying this design methodology as a technology migration tool, and illustrate the failure analysis by comparing the differences in the gm/ID characteristics.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.334/_p
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@ARTICLE{e94-c_3_334,
author={Takayuki KONISHI, Kenji INAZU, Jun Gyu LEE, Masanori NATSUI, Shoichi MASUI, Boris MURMANN, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology},
year={2011},
volume={E94-C},
number={3},
pages={334-345},
abstract={We propose a design optimization flow for a high-speed and low-power operational transconductance amplifier (OTA) using a gm/ID lookup table design methodology in scaled CMOS. This methodology advantages from using gm/ID as a primary design parameter to consider all operation regions including strong, moderate, and weak inversion regions, and enables the lowest power design. SPICE-based lookup table approach is employed to optimize the operation region specified by the gm/ID with sufficient accuracy for short-channel transistors. The optimized design flow features 1) a proposal of the worst-case design scenario for specification and gm/ID lookup table generations from worst-case SPICE simulations, 2) an optimization procedure accomplished by the combination of analytical and simulation-based approaches in order to eliminate tweaking of circuit parameters, and 3) an additional use of gm/ID subplots to take second-order effects into account. A gain-boosted folded-cascode OTA for a switched capacitor circuit is adopted as a target topology to explore the effectiveness of the proposed design methodology for a circuit with complex topology. Analytical expressions of the gain-boosted folded-cascode OTA in terms of DC gain, frequency response and output noise are presented, and detailed optimization of gm/IDs as well as circuit parameters are illustrated. The optimization flow is verified for the application to a residue amplifier in a 10-bit 125 MS/s pipeline A/D converter implemented in a 0.18 µm CMOS technology. The optimized circuit satisfies the required specification for all corner simulations without additional tweaking of circuit parameters. We finally explore the possibility of applying this design methodology as a technology migration tool, and illustrate the failure analysis by comparing the differences in the gm/ID characteristics.},
keywords={},
doi={10.1587/transele.E94.C.334},
ISSN={1745-1353},
month={March},}
부
TY - JOUR
TI - Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology
T2 - IEICE TRANSACTIONS on Electronics
SP - 334
EP - 345
AU - Takayuki KONISHI
AU - Kenji INAZU
AU - Jun Gyu LEE
AU - Masanori NATSUI
AU - Shoichi MASUI
AU - Boris MURMANN
PY - 2011
DO - 10.1587/transele.E94.C.334
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2011
AB - We propose a design optimization flow for a high-speed and low-power operational transconductance amplifier (OTA) using a gm/ID lookup table design methodology in scaled CMOS. This methodology advantages from using gm/ID as a primary design parameter to consider all operation regions including strong, moderate, and weak inversion regions, and enables the lowest power design. SPICE-based lookup table approach is employed to optimize the operation region specified by the gm/ID with sufficient accuracy for short-channel transistors. The optimized design flow features 1) a proposal of the worst-case design scenario for specification and gm/ID lookup table generations from worst-case SPICE simulations, 2) an optimization procedure accomplished by the combination of analytical and simulation-based approaches in order to eliminate tweaking of circuit parameters, and 3) an additional use of gm/ID subplots to take second-order effects into account. A gain-boosted folded-cascode OTA for a switched capacitor circuit is adopted as a target topology to explore the effectiveness of the proposed design methodology for a circuit with complex topology. Analytical expressions of the gain-boosted folded-cascode OTA in terms of DC gain, frequency response and output noise are presented, and detailed optimization of gm/IDs as well as circuit parameters are illustrated. The optimization flow is verified for the application to a residue amplifier in a 10-bit 125 MS/s pipeline A/D converter implemented in a 0.18 µm CMOS technology. The optimized circuit satisfies the required specification for all corner simulations without additional tweaking of circuit parameters. We finally explore the possibility of applying this design methodology as a technology migration tool, and illustrate the failure analysis by comparing the differences in the gm/ID characteristics.
ER -