The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
반도체 제조에서 수율 개선을 가속화하기 위해서는 제품마다 다른 체계적 결함, 파라메트릭 결함 등 제품별 불량의 근본 원인을 예방하는 것이 중요합니다. 여기서는 실제 실패 비트 서명(FBS)과 무작위 결함으로 인해 예측된 FBS 간의 차이를 추정하여 제품별 실패를 조사하는 방법을 제안합니다. 이러한 차이를 정확하게 추정하기 위해 우리는 각 FBS의 임계 영역을 추출하는 새로운 알고리즘을 개발했습니다. FBS의 총 실패율 오류는 다음 범위 내에 있습니다.
Chizu MATSUMOTO
Yuichi HAMAMURA
Yoshiyuki TSUNODA
Hiroshi UOZAKI
Isao MIYAZAKI
Shiro KAMOHARA
Yoshiyuki KANEKO
Kenji KANAMITSU
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Chizu MATSUMOTO, Yuichi HAMAMURA, Yoshiyuki TSUNODA, Hiroshi UOZAKI, Isao MIYAZAKI, Shiro KAMOHARA, Yoshiyuki KANEKO, Kenji KANAMITSU, "A New Critical Area Simulation Algorithm and Its Application for Failing Bit Analysis" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 3, pp. 353-360, March 2011, doi: 10.1587/transele.E94.C.353.
Abstract: In order to accelerate yield improvement in semiconductor manufacturing, it is important to prevent the root causes of product-specific failures, such as systematic defects and parametric defects, which are different for each product. We herein propose a method for the investigation of product-specific failures by estimating differences between the actual failing bit signatures (FBSs) and the predicted FBSs caused by random defects. In order to estimate these differences accurately, we have developed a novel algorithm by which to extract the critical area for each FBS. The total failure rate errors of FBSs are within
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.353/_p
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@ARTICLE{e94-c_3_353,
author={Chizu MATSUMOTO, Yuichi HAMAMURA, Yoshiyuki TSUNODA, Hiroshi UOZAKI, Isao MIYAZAKI, Shiro KAMOHARA, Yoshiyuki KANEKO, Kenji KANAMITSU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A New Critical Area Simulation Algorithm and Its Application for Failing Bit Analysis},
year={2011},
volume={E94-C},
number={3},
pages={353-360},
abstract={In order to accelerate yield improvement in semiconductor manufacturing, it is important to prevent the root causes of product-specific failures, such as systematic defects and parametric defects, which are different for each product. We herein propose a method for the investigation of product-specific failures by estimating differences between the actual failing bit signatures (FBSs) and the predicted FBSs caused by random defects. In order to estimate these differences accurately, we have developed a novel algorithm by which to extract the critical area for each FBS. The total failure rate errors of FBSs are within
keywords={},
doi={10.1587/transele.E94.C.353},
ISSN={1745-1353},
month={March},}
부
TY - JOUR
TI - A New Critical Area Simulation Algorithm and Its Application for Failing Bit Analysis
T2 - IEICE TRANSACTIONS on Electronics
SP - 353
EP - 360
AU - Chizu MATSUMOTO
AU - Yuichi HAMAMURA
AU - Yoshiyuki TSUNODA
AU - Hiroshi UOZAKI
AU - Isao MIYAZAKI
AU - Shiro KAMOHARA
AU - Yoshiyuki KANEKO
AU - Kenji KANAMITSU
PY - 2011
DO - 10.1587/transele.E94.C.353
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2011
AB - In order to accelerate yield improvement in semiconductor manufacturing, it is important to prevent the root causes of product-specific failures, such as systematic defects and parametric defects, which are different for each product. We herein propose a method for the investigation of product-specific failures by estimating differences between the actual failing bit signatures (FBSs) and the predicted FBSs caused by random defects. In order to estimate these differences accurately, we have developed a novel algorithm by which to extract the critical area for each FBS. The total failure rate errors of FBSs are within
ER -