The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 ROI 기반의 H.264 인코더와 ROI 검출 알고리즘의 VLSI 아키텍처를 제안한다. ROI 기반 비디오 코딩 시스템에서 ROI를 검출하는 전처리 장치는 낮은 전력 요구 사항으로 인해 계산 복잡도가 낮아야 합니다. ROI의 매크로블록(MB)은 ROI 검출기와 H.264 인코더의 MB 레벨 파이프라이닝을 만족시키기 위해 H.264 인코딩과 동일한 순서로 순차적으로 검출됩니다. ROI 검출은 ROI 윤곽 템플릿을 사용하는 새로운 추정 및 검증 프로세스에서 수행됩니다. 제안된 아키텍처는 각 프레임에서 단일 ROI 또는 다중 ROI를 감지하도록 구성할 수 있으며 단일 감지 모드의 처리량은 다중 감지 모드의 5.5배입니다. ROI에서 MB의 98.01%와 97.89%는 단일 감지 모드와 다중 감지 모드에서 각각 감지될 수 있습니다. 제안된 아키텍처의 하드웨어 비용은 4.68k 게이트에 불과합니다. 감지 속도는 753mW의 전력 소비로 다중 감지 모드에서 작동 주파수 200MHz에서 CIF 형식 비디오의 경우 0.47fps입니다. 이전의 비디오 코딩 응용을 위한 빠른 ROI 감지 알고리즘과 비교하여 제안된 아키텍처는 더 정확하고 더 작은 ROI를 얻습니다. 따라서 H.264 인코더에서는 보다 효율적인 ROI 기반 계산 복잡성 및 압축 효율성 최적화를 구현할 수 있습니다.
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Tianruo ZHANG, Chen LIU, Minghui WANG, Satoshi GOTO, "Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 4, pp. 401-410, April 2011, doi: 10.1587/transele.E94.C.401.
Abstract: This paper proposes a region-of-interest (ROI) based H.264 encoder and the VLSI architecture of the ROI detection algorithm. In ROI based video coding system, pre-processing unit to detect ROI should only introduce low computational complexity overhead due to the low power requirement. The Macroblocks (MBs) in ROIs are detected sequentially in the same order of H.264 encoding to satisfy the MB level pipelining of ROI detector and H.264 encoder. ROI detection is performed in a novel estimation-and-verification process with an ROI contour template. Proposed architecture can be configured to detect either single ROI or multiple ROIs in each frame and the throughput of single detection mode is 5.5 times of multiple detection mode. 98.01% and 97.89% of MBs in ROIs can be detected in single and multiple detection modes respectively. Hardware cost of proposed architecture is only 4.68 k gates. Detection speed is 753 fps for CIF format video at the operation frequency of 200 MHz in multiple detection mode with power consumption of 0.47 mW. Compared with previous fast ROI detection algorithms for video coding application, the proposed architecture obtains more accurate and smaller ROI. Therefore, more efficient ROI based computation complexity and compression efficiency optimization can be implemented in H.264 encoder.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.401/_p
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@ARTICLE{e94-c_4_401,
author={Tianruo ZHANG, Chen LIU, Minghui WANG, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining},
year={2011},
volume={E94-C},
number={4},
pages={401-410},
abstract={This paper proposes a region-of-interest (ROI) based H.264 encoder and the VLSI architecture of the ROI detection algorithm. In ROI based video coding system, pre-processing unit to detect ROI should only introduce low computational complexity overhead due to the low power requirement. The Macroblocks (MBs) in ROIs are detected sequentially in the same order of H.264 encoding to satisfy the MB level pipelining of ROI detector and H.264 encoder. ROI detection is performed in a novel estimation-and-verification process with an ROI contour template. Proposed architecture can be configured to detect either single ROI or multiple ROIs in each frame and the throughput of single detection mode is 5.5 times of multiple detection mode. 98.01% and 97.89% of MBs in ROIs can be detected in single and multiple detection modes respectively. Hardware cost of proposed architecture is only 4.68 k gates. Detection speed is 753 fps for CIF format video at the operation frequency of 200 MHz in multiple detection mode with power consumption of 0.47 mW. Compared with previous fast ROI detection algorithms for video coding application, the proposed architecture obtains more accurate and smaller ROI. Therefore, more efficient ROI based computation complexity and compression efficiency optimization can be implemented in H.264 encoder.},
keywords={},
doi={10.1587/transele.E94.C.401},
ISSN={1745-1353},
month={April},}
부
TY - JOUR
TI - Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining
T2 - IEICE TRANSACTIONS on Electronics
SP - 401
EP - 410
AU - Tianruo ZHANG
AU - Chen LIU
AU - Minghui WANG
AU - Satoshi GOTO
PY - 2011
DO - 10.1587/transele.E94.C.401
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - This paper proposes a region-of-interest (ROI) based H.264 encoder and the VLSI architecture of the ROI detection algorithm. In ROI based video coding system, pre-processing unit to detect ROI should only introduce low computational complexity overhead due to the low power requirement. The Macroblocks (MBs) in ROIs are detected sequentially in the same order of H.264 encoding to satisfy the MB level pipelining of ROI detector and H.264 encoder. ROI detection is performed in a novel estimation-and-verification process with an ROI contour template. Proposed architecture can be configured to detect either single ROI or multiple ROIs in each frame and the throughput of single detection mode is 5.5 times of multiple detection mode. 98.01% and 97.89% of MBs in ROIs can be detected in single and multiple detection modes respectively. Hardware cost of proposed architecture is only 4.68 k gates. Detection speed is 753 fps for CIF format video at the operation frequency of 200 MHz in multiple detection mode with power consumption of 0.47 mW. Compared with previous fast ROI detection algorithms for video coding application, the proposed architecture obtains more accurate and smaller ROI. Therefore, more efficient ROI based computation complexity and compression efficiency optimization can be implemented in H.264 encoder.
ER -