The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
H.264/AVC의 인트라 코딩은 비디오 압축 효율성을 크게 향상시킵니다. 그러나 H.264에서는 인트라 예측의 높은 데이터 의존성으로 인해 파이프라이닝과 병렬 처리 기술을 모두 적용하는 데 제한이 있습니다. 게다가 블록/MB 수준 재구성 루프가 길기 때문에 높은 하드웨어 활용도와 처리량을 얻기가 어렵습니다. 본 논문에서는 H.264/AVC High Profile을 지원할 수 있는 고성능 인트라 예측 아키텍처를 제안한다. 제안된 MB/블록 공동 재정렬은 데이터 종속성을 방지하고 파이프라인 활용도를 향상시킬 수 있습니다. 따라서 실시간 4096의 타이밍 제약
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부
Gang HE, Dajiang ZHOU, Jinjia ZHOU, Tianruo ZHANG, Satoshi GOTO, "A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 4, pp. 419-427, April 2011, doi: 10.1587/transele.E94.C.419.
Abstract: Intra coding in H.264/AVC significantly enhances video compression efficiency. However, due to the high data dependency of intra prediction in H.264, both pipelining and parallel processing techniques are limited to be applied. Moreover, it is difficult to get high hardware utilization and throughput because of the long block/MB-level reconstruction loops. This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 4096
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.419/_p
부
@ARTICLE{e94-c_4_419,
author={Gang HE, Dajiang ZHOU, Jinjia ZHOU, Tianruo ZHANG, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder},
year={2011},
volume={E94-C},
number={4},
pages={419-427},
abstract={Intra coding in H.264/AVC significantly enhances video compression efficiency. However, due to the high data dependency of intra prediction in H.264, both pipelining and parallel processing techniques are limited to be applied. Moreover, it is difficult to get high hardware utilization and throughput because of the long block/MB-level reconstruction loops. This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 4096
keywords={},
doi={10.1587/transele.E94.C.419},
ISSN={1745-1353},
month={April},}
부
TY - JOUR
TI - A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder
T2 - IEICE TRANSACTIONS on Electronics
SP - 419
EP - 427
AU - Gang HE
AU - Dajiang ZHOU
AU - Jinjia ZHOU
AU - Tianruo ZHANG
AU - Satoshi GOTO
PY - 2011
DO - 10.1587/transele.E94.C.419
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - Intra coding in H.264/AVC significantly enhances video compression efficiency. However, due to the high data dependency of intra prediction in H.264, both pipelining and parallel processing techniques are limited to be applied. Moreover, it is difficult to get high hardware utilization and throughput because of the long block/MB-level reconstruction loops. This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 4096
ER -