The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
NBTI(네거티브 바이어스 온도 불안정성)는 고급 기술의 주요 신뢰성 문제 중 하나입니다. NBTI는 PMOS 트랜지스터에서 문턱 전압 이동을 유발합니다. PMOS 트랜지스터가 음의 전압으로 바이어스되면 임계 전압은 음의 전압으로 이동합니다. 반면, PMOS 트랜지스터가 양으로 바이어스되면 문턱 전압이 회복됩니다. SRAM 셀에서는 NBTI로 인해 부하 PMOS 트랜지스터의 임계 전압이 저하됩니다. 성능 저하는 6T SRAM 셀의 읽기 안정성을 측정하는 SNM(정적 잡음 마진)에 영향을 미칩니다. 본 논문에서는 SRAM 셀의 NBTI 저하와 동적 스트레스 및 회복 조건 간의 관계에 대해 논의합니다. 두 가지 중요한 특성이 있습니다. 하나는 PMOS 트랜지스터가 음으로 바이어스되는 비율로 정의되는 스트레스 확률입니다. 다른 하나는 SRAM 값의 전환 간격으로 정의되는 스트레스 및 복구 주기입니다. 우리의 관찰에 따르면 NBTI 저하를 완화하려면 스트레스 확률이 작아야 하며 스트레스 및 복구 주기가 10msec보다 짧아야 합니다. 관찰 결과를 바탕으로 우리는 응력 확률을 50%에 가깝게 만드는 새로운 셀 뒤집기 기술을 제안합니다. 또한 셀 플리핑 기법을 파일 등록 및 캐시 메모리에 적용한 사례 연구 결과를 보여줍니다.
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Yuji KUNITAKE, Toshinori SATO, Hiroto YASUURA, "Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 4, pp. 520-529, April 2011, doi: 10.1587/transele.E94.C.520.
Abstract: Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage shift in a PMOS transistor. When the PMOS transistor is biased to negative voltage, threshold voltage shifts to negatively. On the other hand, the threshold voltage recovers if the PMOS transistor is positively biased. In an SRAM cell, due to NBTI, threshold voltage degrades in the load PMOS transistors. The degradation has the impact on Static Noise Margin (SNM), which is a measure of read stability of a 6-T SRAM cell. In this paper, we discuss the relationship between NBTI degradation in an SRAM cell and the dynamic stress and recovery condition. There are two important characteristics. One is a stress probability, which is defined as the rate that the PMOS transistor is negatively biased. The other is a stress and recovery cycle, which is defined as the switching interval of an SRAM value. In our observations, in order to mitigate the NBTI degradation, the stress probability should be small and the stress and recovery cycle should be shorter than 10 msec. Based on the observations, we propose a novel cell-flipping technique, which makes the stress probability close to 50%. In addition, we show results of the case studies, which apply the cell-flipping technique to register file and cache memories.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.520/_p
부
@ARTICLE{e94-c_4_520,
author={Yuji KUNITAKE, Toshinori SATO, Hiroto YASUURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI},
year={2011},
volume={E94-C},
number={4},
pages={520-529},
abstract={Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage shift in a PMOS transistor. When the PMOS transistor is biased to negative voltage, threshold voltage shifts to negatively. On the other hand, the threshold voltage recovers if the PMOS transistor is positively biased. In an SRAM cell, due to NBTI, threshold voltage degrades in the load PMOS transistors. The degradation has the impact on Static Noise Margin (SNM), which is a measure of read stability of a 6-T SRAM cell. In this paper, we discuss the relationship between NBTI degradation in an SRAM cell and the dynamic stress and recovery condition. There are two important characteristics. One is a stress probability, which is defined as the rate that the PMOS transistor is negatively biased. The other is a stress and recovery cycle, which is defined as the switching interval of an SRAM value. In our observations, in order to mitigate the NBTI degradation, the stress probability should be small and the stress and recovery cycle should be shorter than 10 msec. Based on the observations, we propose a novel cell-flipping technique, which makes the stress probability close to 50%. In addition, we show results of the case studies, which apply the cell-flipping technique to register file and cache memories.},
keywords={},
doi={10.1587/transele.E94.C.520},
ISSN={1745-1353},
month={April},}
부
TY - JOUR
TI - Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI
T2 - IEICE TRANSACTIONS on Electronics
SP - 520
EP - 529
AU - Yuji KUNITAKE
AU - Toshinori SATO
AU - Hiroto YASUURA
PY - 2011
DO - 10.1587/transele.E94.C.520
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage shift in a PMOS transistor. When the PMOS transistor is biased to negative voltage, threshold voltage shifts to negatively. On the other hand, the threshold voltage recovers if the PMOS transistor is positively biased. In an SRAM cell, due to NBTI, threshold voltage degrades in the load PMOS transistors. The degradation has the impact on Static Noise Margin (SNM), which is a measure of read stability of a 6-T SRAM cell. In this paper, we discuss the relationship between NBTI degradation in an SRAM cell and the dynamic stress and recovery condition. There are two important characteristics. One is a stress probability, which is defined as the rate that the PMOS transistor is negatively biased. The other is a stress and recovery cycle, which is defined as the switching interval of an SRAM value. In our observations, in order to mitigate the NBTI degradation, the stress probability should be small and the stress and recovery cycle should be shorter than 10 msec. Based on the observations, we propose a novel cell-flipping technique, which makes the stress probability close to 50%. In addition, we show results of the case studies, which apply the cell-flipping technique to register file and cache memories.
ER -