The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
균형 잡힌 푸시-푸시 주파수 더블러는 높은 기본 주파수 억제 및 높은 변환 이득을 통해 0.25GHz~22GHz에서 작동하는 29μm SOI(Silicon on Insulator) SiGe BiCMOS 기술에서 시연되었습니다. 직렬 LC 공진기 회로는 더블러 코어 회로의 차동 출력과 병렬로 연결됩니다. LC 공진기는 기본 주파수 억제를 개선하는 데 효과적입니다. 또한 LC 공진기는 더블러 코어의 출력과 출력 버퍼 증폭기의 입력 간의 매칭 회로로 작동하여 전체 회로의 변환 이득을 증가시킵니다. 46dBc보다 큰 측정된 기본 주파수 억제는 10~22GHz의 출력 주파수 대역에서 -29dBm의 입력 전력에서 달성됩니다. 또한 66dBc의 최대 기본 주파수 억제는 13GHz의 입력 주파수와 -10dBm의 입력 전력에서 달성됩니다. 주파수 배율기는 3.3V의 공급 전압에서 작동합니다.
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Jiangtao SUN, Qing LIU, Yong-Ju SUH, Takayuki SHIBATA, Toshihiko YOSHIMASU, "A 66-dBc Fundamental Suppression Frequency Doubler IC for UWB Sensor Applications" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 4, pp. 575-581, April 2011, doi: 10.1587/transele.E94.C.575.
Abstract: A balanced push-push frequency doubler has been demonstrated in 0.25-µm SOI (Silicon on Insulator) SiGe BiCMOS technology operating from 22 GHz to 29 GHz with high fundamental frequency suppression and high conversion gain. A series LC resonator circuit is connected in parallel with the differential outputs of the doubler core circuit. The LC resonator is effective to improve the fundamental frequency suppression. In addition, the LC resonator works as a matching circuit between the output of the doubler core and the input of the output buffer amplifier, which increases the conversion gain of the whole circuit. A measured fundamental frequency suppression of greater than 46 dBc is achieved at an input power of -10 dBm in the output frequency band of 22-29 GHz. Moreover, maximum fundamental frequency suppression of 66 dBc is achieved at an input frequency of 13 GHz and an input power of -10 dBm. The frequency doubler works at a supply voltage of 3.3 V.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.575/_p
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@ARTICLE{e94-c_4_575,
author={Jiangtao SUN, Qing LIU, Yong-Ju SUH, Takayuki SHIBATA, Toshihiko YOSHIMASU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 66-dBc Fundamental Suppression Frequency Doubler IC for UWB Sensor Applications},
year={2011},
volume={E94-C},
number={4},
pages={575-581},
abstract={A balanced push-push frequency doubler has been demonstrated in 0.25-µm SOI (Silicon on Insulator) SiGe BiCMOS technology operating from 22 GHz to 29 GHz with high fundamental frequency suppression and high conversion gain. A series LC resonator circuit is connected in parallel with the differential outputs of the doubler core circuit. The LC resonator is effective to improve the fundamental frequency suppression. In addition, the LC resonator works as a matching circuit between the output of the doubler core and the input of the output buffer amplifier, which increases the conversion gain of the whole circuit. A measured fundamental frequency suppression of greater than 46 dBc is achieved at an input power of -10 dBm in the output frequency band of 22-29 GHz. Moreover, maximum fundamental frequency suppression of 66 dBc is achieved at an input frequency of 13 GHz and an input power of -10 dBm. The frequency doubler works at a supply voltage of 3.3 V.},
keywords={},
doi={10.1587/transele.E94.C.575},
ISSN={1745-1353},
month={April},}
부
TY - JOUR
TI - A 66-dBc Fundamental Suppression Frequency Doubler IC for UWB Sensor Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 575
EP - 581
AU - Jiangtao SUN
AU - Qing LIU
AU - Yong-Ju SUH
AU - Takayuki SHIBATA
AU - Toshihiko YOSHIMASU
PY - 2011
DO - 10.1587/transele.E94.C.575
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - A balanced push-push frequency doubler has been demonstrated in 0.25-µm SOI (Silicon on Insulator) SiGe BiCMOS technology operating from 22 GHz to 29 GHz with high fundamental frequency suppression and high conversion gain. A series LC resonator circuit is connected in parallel with the differential outputs of the doubler core circuit. The LC resonator is effective to improve the fundamental frequency suppression. In addition, the LC resonator works as a matching circuit between the output of the doubler core and the input of the output buffer amplifier, which increases the conversion gain of the whole circuit. A measured fundamental frequency suppression of greater than 46 dBc is achieved at an input power of -10 dBm in the output frequency band of 22-29 GHz. Moreover, maximum fundamental frequency suppression of 66 dBc is achieved at an input frequency of 13 GHz and an input power of -10 dBm. The frequency doubler works at a supply voltage of 3.3 V.
ER -