The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 증폭 및 래치 동작 모두에 대해 적시에 예약된 고속 단일 스테이지 래치 비교기를 제시합니다. 높은 비교율에서 원하는 전력 소비 외에 작은 활성 영역과 간단한 스위칭 전략으로 인해 제안된 비교기는 고속 플래시 A/D 변환기에 반복적으로 사용될 수 있습니다. 게인 강화 외에 반동 소음 제거 전략도 도입됐다. 저전력 유지 판독 회로가 제공됩니다. 레이아웃 후 시뮬레이션 결과는 500 µm CMOS 기술의 TSMC 모델을 사용하여 5 v 피크 대 피크 입력 신호 범위에 대해 1.6 mv 해상도와 600 v 전원 공급 장치에서 3.3 µw 전력 소비로 0.35 MS/s 비교 속도를 확인합니다. 제안된 비교기와 판독 회로의 총 활성 영역은 약 300μm입니다.2.
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Sarang KAZEMINIA, Morteza MOUSAZADEH, Kayrollah HADIDI, Abdollah KHOEI, "A 500 MS/s 600 µW 300 µm2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 4, pp. 635-640, April 2011, doi: 10.1587/transele.E94.C.635.
Abstract: This paper presents a high speed single-stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area and simple switching strategy besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding read-out circuit is presented. Post-Layout simulation results confirm 500 MS/s comparison rate with 5 mv resolution for a 1.6 v peak-to-peak input signal range and 600 µw power consumption from a 3.3 v power supply by using TSMC model of 0.35 µm CMOS technology. Total active area of proposed comparator and read-out circuit is about 300 µm2.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.635/_p
부
@ARTICLE{e94-c_4_635,
author={Sarang KAZEMINIA, Morteza MOUSAZADEH, Kayrollah HADIDI, Abdollah KHOEI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 500 MS/s 600 µW 300 µm2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process},
year={2011},
volume={E94-C},
number={4},
pages={635-640},
abstract={This paper presents a high speed single-stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area and simple switching strategy besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding read-out circuit is presented. Post-Layout simulation results confirm 500 MS/s comparison rate with 5 mv resolution for a 1.6 v peak-to-peak input signal range and 600 µw power consumption from a 3.3 v power supply by using TSMC model of 0.35 µm CMOS technology. Total active area of proposed comparator and read-out circuit is about 300 µm2.},
keywords={},
doi={10.1587/transele.E94.C.635},
ISSN={1745-1353},
month={April},}
부
TY - JOUR
TI - A 500 MS/s 600 µW 300 µm2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process
T2 - IEICE TRANSACTIONS on Electronics
SP - 635
EP - 640
AU - Sarang KAZEMINIA
AU - Morteza MOUSAZADEH
AU - Kayrollah HADIDI
AU - Abdollah KHOEI
PY - 2011
DO - 10.1587/transele.E94.C.635
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - This paper presents a high speed single-stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area and simple switching strategy besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding read-out circuit is presented. Post-Layout simulation results confirm 500 MS/s comparison rate with 5 mv resolution for a 1.6 v peak-to-peak input signal range and 600 µw power consumption from a 3.3 v power supply by using TSMC model of 0.35 µm CMOS technology. Total active area of proposed comparator and read-out circuit is about 300 µm2.
ER -