The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
본 논문에서는 저전력 파이프라인 아날로그-디지털 변환기(ADC)를 구현하기 위한 두 가지 기술을 제안합니다. 첫째, 하프레이트 프런트 엔드 SHA(샘플 앤 홀드 증폭기) 없이 스위치드 커패시터 회로에서 연산 증폭기의 유한 이득 오류를 보상하기 위해 시간 인터리브 상관 이중 샘플링(CDS) 기술이 제안되었습니다. 따라서 저이득 증폭기와 SHA 없는 아키텍처를 사용하면 파이프라인 ADC의 전력 소비를 효과적으로 줄일 수 있습니다. 둘째, 파이프라인 ADC의 백엔드 파이프라인 단계는 제안된 파이프라인 ADC의 전력 소비를 더욱 줄이기 위해 연산 증폭기 대신 저전력 시간 인터리브 연속 근사(SA) ADC를 사용하여 구현됩니다. 9비트, 100MS/s 하이브리드 파이프라인 SA ADC는 TSMC 0.13μm 삼중 웰 1P8M CMOS 프로세스에서 구현됩니다. ADC는 62.15MS/s 샘플링 속도에서 50.85MHz 입력 주파수에 대해 2dB의 SFDR(스퓨리어스 없는 동적 범위)과 100dB의 SNDR(신호 대 잡음 왜곡 비율)을 달성합니다. 전력 소비는 21.2V 공급 장치에서 1.2mW입니다. ADC의 핵심 영역은 1.6mm입니다.2.
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부
Jin-Fu LIN, Soon-Jyh CHANG, "A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 1, pp. 89-101, January 2011, doi: 10.1587/transele.E94.C.89.
Abstract: In this paper, two techniques for implementing a low-power pipelined analog-to-digital converter (ADC) are proposed. First, the time-interleaved correlated double sampling (CDS) technique is proposed to compensate the finite gain error of operational amplifiers in switched-capacitor circuits without a half-rate front-end sample-and-hold amplifier (SHA). Therefore, low-gain amplifiers and the SHA-less architecture can be used to effectively reduce power consumption of a pipelined ADC. Second, the back-end pipelined stages of a pipelined ADC are implemented using a low-power time-interleaved successive approximation (SA) ADC rather than operational amplifiers to further reduce the power consumption of the proposed pipelined ADC. A 9-bit, 100-MS/s hybrid pipelined-SA ADC is implemented in the TSMC 0.13 µm triple-well 1P8M CMOS process. The ADC achieves a spurious free dynamic range (SFDR) of 62.15 dB and a signal-to-noise distortion ratio (SNDR) of 50.85-dB for 2-MHz input frequency at a 100-MS/s sampling rate. The power consumption is 21.2 mW from a 1.2 V supply. The core area of the ADC is 1.6 mm2.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.89/_p
부
@ARTICLE{e94-c_1_89,
author={Jin-Fu LIN, Soon-Jyh CHANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages},
year={2011},
volume={E94-C},
number={1},
pages={89-101},
abstract={In this paper, two techniques for implementing a low-power pipelined analog-to-digital converter (ADC) are proposed. First, the time-interleaved correlated double sampling (CDS) technique is proposed to compensate the finite gain error of operational amplifiers in switched-capacitor circuits without a half-rate front-end sample-and-hold amplifier (SHA). Therefore, low-gain amplifiers and the SHA-less architecture can be used to effectively reduce power consumption of a pipelined ADC. Second, the back-end pipelined stages of a pipelined ADC are implemented using a low-power time-interleaved successive approximation (SA) ADC rather than operational amplifiers to further reduce the power consumption of the proposed pipelined ADC. A 9-bit, 100-MS/s hybrid pipelined-SA ADC is implemented in the TSMC 0.13 µm triple-well 1P8M CMOS process. The ADC achieves a spurious free dynamic range (SFDR) of 62.15 dB and a signal-to-noise distortion ratio (SNDR) of 50.85-dB for 2-MHz input frequency at a 100-MS/s sampling rate. The power consumption is 21.2 mW from a 1.2 V supply. The core area of the ADC is 1.6 mm2.},
keywords={},
doi={10.1587/transele.E94.C.89},
ISSN={1745-1353},
month={January},}
부
TY - JOUR
TI - A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages
T2 - IEICE TRANSACTIONS on Electronics
SP - 89
EP - 101
AU - Jin-Fu LIN
AU - Soon-Jyh CHANG
PY - 2011
DO - 10.1587/transele.E94.C.89
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2011
AB - In this paper, two techniques for implementing a low-power pipelined analog-to-digital converter (ADC) are proposed. First, the time-interleaved correlated double sampling (CDS) technique is proposed to compensate the finite gain error of operational amplifiers in switched-capacitor circuits without a half-rate front-end sample-and-hold amplifier (SHA). Therefore, low-gain amplifiers and the SHA-less architecture can be used to effectively reduce power consumption of a pipelined ADC. Second, the back-end pipelined stages of a pipelined ADC are implemented using a low-power time-interleaved successive approximation (SA) ADC rather than operational amplifiers to further reduce the power consumption of the proposed pipelined ADC. A 9-bit, 100-MS/s hybrid pipelined-SA ADC is implemented in the TSMC 0.13 µm triple-well 1P8M CMOS process. The ADC achieves a spurious free dynamic range (SFDR) of 62.15 dB and a signal-to-noise distortion ratio (SNDR) of 50.85-dB for 2-MHz input frequency at a 100-MS/s sampling rate. The power consumption is 21.2 mW from a 1.2 V supply. The core area of the ADC is 1.6 mm2.
ER -