The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
클럭이 임의의 타이밍에 각 레지스터에 입력될 수 있다는 가정하에 회로 동작과 토폴로지를 유지하면서 레지스터 재배치를 통해 최소 실행 가능 클럭 주기가 줄어들 수 있습니다. 그러나 실현 가능한 최소 클럭 주기가 줄어들면 레지스터 수가 늘어나는 경향이 있습니다. 본 논문에서는 목표 클럭 주기를 유지하면서 레지스터 수를 줄이는 게이트 레벨 레지스터 재배치 방법을 제안한다. 실험에서 제안한 방법은 대부분의 회로에서 실제 시간에 레지스터 수를 줄였다.
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Yukihide KOHIRA, Atsushi TAKAHASHI, "A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 10, pp. 3030-3037, October 2008, doi: 10.1093/ietfec/e91-a.10.3030.
Abstract: Under the assumption that the clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period might be reduced by register relocation while maintaining the circuit behavior and topology. However, if the minimum feasible clock period is reduced, then the number of registers tends to be increased. In this paper, we propose a gate-level register relocation method that reduces the number of registers while keeping the target clock period. In experiments, the proposed method reduces the number of registers in the practical time in most circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.10.3030/_p
부
@ARTICLE{e91-a_10_3030,
author={Yukihide KOHIRA, Atsushi TAKAHASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework},
year={2008},
volume={E91-A},
number={10},
pages={3030-3037},
abstract={Under the assumption that the clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period might be reduced by register relocation while maintaining the circuit behavior and topology. However, if the minimum feasible clock period is reduced, then the number of registers tends to be increased. In this paper, we propose a gate-level register relocation method that reduces the number of registers while keeping the target clock period. In experiments, the proposed method reduces the number of registers in the practical time in most circuits.},
keywords={},
doi={10.1093/ietfec/e91-a.10.3030},
ISSN={1745-1337},
month={October},}
부
TY - JOUR
TI - A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3030
EP - 3037
AU - Yukihide KOHIRA
AU - Atsushi TAKAHASHI
PY - 2008
DO - 10.1093/ietfec/e91-a.10.3030
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 2008
AB - Under the assumption that the clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period might be reduced by register relocation while maintaining the circuit behavior and topology. However, if the minimum feasible clock period is reduced, then the number of registers tends to be increased. In this paper, we propose a gate-level register relocation method that reduces the number of registers while keeping the target clock period. In experiments, the proposed method reduces the number of registers in the practical time in most circuits.
ER -