The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
제조 공정이 미세화되고 공급 전압이 낮아짐에 따라 제조 가변성이 회로 성능에 미치는 영향이 커지고 있습니다. 본 논문에서는 클록 스큐를 줄이는 데 효과적이라고 생각되는 메쉬 스타일 클록 분포에 중점을 두고 제조 및 설계 가변성을 고려하여 클록 스큐를 평가합니다. MOS 트랜지스터 변동(무작위 및 공간 상관 변동)과 불균일 플립플롭(FF) 배치를 고려하면 공간 상관 변동과 심한 불균일 FF 분포가 클록 스큐의 주요 원인이 될 수 있음을 보여줍니다. 또한 설계 매개변수에 대한 클록 스큐의 종속성을 조사하고 클록 메시가 더 미세하다고 해서 클록 스큐가 반드시 감소하는 것은 아니라는 사실을 밝힙니다.
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Shinya ABE, Masanori HASHIMOTO, Takao ONOYE, "Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 12, pp. 3481-3487, December 2008, doi: 10.1093/ietfec/e91-a.12.3481.
Abstract: Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on mesh-style clock distribution which is believed to be effective for reducing clock skew, and we evaluate clock skew considering manufacturing and design variabilities. Considering MOS transistor variation -- random and spatially-correlated variation -- and non-uniform flip-flop (FF) placement, we demonstrate that spatially-correlated variation and severe non-uniform FF distribution can be major sources of clock skew. We also examine the dependency of clock skew on design parameters, and reveal that finer clock mesh does not necessarily reduce clock skew.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.12.3481/_p
부
@ARTICLE{e91-a_12_3481,
author={Shinya ABE, Masanori HASHIMOTO, Takao ONOYE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution},
year={2008},
volume={E91-A},
number={12},
pages={3481-3487},
abstract={Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on mesh-style clock distribution which is believed to be effective for reducing clock skew, and we evaluate clock skew considering manufacturing and design variabilities. Considering MOS transistor variation -- random and spatially-correlated variation -- and non-uniform flip-flop (FF) placement, we demonstrate that spatially-correlated variation and severe non-uniform FF distribution can be major sources of clock skew. We also examine the dependency of clock skew on design parameters, and reveal that finer clock mesh does not necessarily reduce clock skew.},
keywords={},
doi={10.1093/ietfec/e91-a.12.3481},
ISSN={1745-1337},
month={December},}
부
TY - JOUR
TI - Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3481
EP - 3487
AU - Shinya ABE
AU - Masanori HASHIMOTO
AU - Takao ONOYE
PY - 2008
DO - 10.1093/ietfec/e91-a.12.3481
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2008
AB - Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on mesh-style clock distribution which is believed to be effective for reducing clock skew, and we evaluate clock skew considering manufacturing and design variabilities. Considering MOS transistor variation -- random and spatially-correlated variation -- and non-uniform flip-flop (FF) placement, we demonstrate that spatially-correlated variation and severe non-uniform FF distribution can be major sources of clock skew. We also examine the dependency of clock skew on design parameters, and reveal that finer clock mesh does not necessarily reduce clock skew.
ER -