The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
더 높은 처리량과 더 낮은 에너지 소비를 위한 새로운 2차원 이산 웨이블릿 변환(XNUMX-DDWT) 병렬 아키텍처가 제안되었습니다. 제안된 아키텍처는 DRAM의 전체 페이지 버스트 액세스를 완전히 활용하고 DRAM 활성화 및 사전 충전 작업 수를 최소화합니다. 시뮬레이션 결과에 따르면 이 아키텍처는 적절한 내부 메모리 비용으로 DRAM 메모리 액세스를 위한 클록 사이클 수는 물론 DRAM 전력 소비도 줄이는 것으로 나타났습니다. 아키텍처의 VLSI 구현을 평가한 결과, 최소 영역 비용으로 행 필터링을 병렬화하여 웨이블릿 필터링의 처리량이 증가하여 DRAM 전체 페이지 버스트 액세스를 활용할 수 있음이 나타났습니다.
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Nozomi ISHIHARA, Koki ABE, "Parallel Architecture for 2-D Discrete Wavelet Transform with Low Energy Consumption" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 8, pp. 2068-2075, August 2008, doi: 10.1093/ietfec/e91-a.8.2068.
Abstract: A novel two-dimensional discrete wavelet transform (2-DDWT) parallel architecture for higher throughput and lower energy consumption is proposed. The proposed architecture fully exploits full-page burst accesses of DRAM and minimizes the number of DRAM activate and precharge operations. Simulation results revealed that the architecture reduces the number of clock cycles for DRAM memory accesses as well as the DRAM power consumption with moderate cost of internal memory. Evaluation of the VLSI implementation of the architecture showed that the throughput of wavelet filtering was increased by parallelizing row filtering with a minimum area cost, thereby enabling DRAM full-page burst accesses to be exploited.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.8.2068/_p
부
@ARTICLE{e91-a_8_2068,
author={Nozomi ISHIHARA, Koki ABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Parallel Architecture for 2-D Discrete Wavelet Transform with Low Energy Consumption},
year={2008},
volume={E91-A},
number={8},
pages={2068-2075},
abstract={A novel two-dimensional discrete wavelet transform (2-DDWT) parallel architecture for higher throughput and lower energy consumption is proposed. The proposed architecture fully exploits full-page burst accesses of DRAM and minimizes the number of DRAM activate and precharge operations. Simulation results revealed that the architecture reduces the number of clock cycles for DRAM memory accesses as well as the DRAM power consumption with moderate cost of internal memory. Evaluation of the VLSI implementation of the architecture showed that the throughput of wavelet filtering was increased by parallelizing row filtering with a minimum area cost, thereby enabling DRAM full-page burst accesses to be exploited.},
keywords={},
doi={10.1093/ietfec/e91-a.8.2068},
ISSN={1745-1337},
month={August},}
부
TY - JOUR
TI - Parallel Architecture for 2-D Discrete Wavelet Transform with Low Energy Consumption
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2068
EP - 2075
AU - Nozomi ISHIHARA
AU - Koki ABE
PY - 2008
DO - 10.1093/ietfec/e91-a.8.2068
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2008
AB - A novel two-dimensional discrete wavelet transform (2-DDWT) parallel architecture for higher throughput and lower energy consumption is proposed. The proposed architecture fully exploits full-page burst accesses of DRAM and minimizes the number of DRAM activate and precharge operations. Simulation results revealed that the architecture reduces the number of clock cycles for DRAM memory accesses as well as the DRAM power consumption with moderate cost of internal memory. Evaluation of the VLSI implementation of the architecture showed that the throughput of wavelet filtering was increased by parallelizing row filtering with a minimum area cost, thereby enabling DRAM full-page burst accesses to be exploited.
ER -